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With over 2000 terms defined and explained, Semiconductor Glossary is the most complete reference in the field of semiconductors on the market today.












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Term (Index) Definition
via 7 hole etched in the interlayer dielectric which is then filled with metal, usually tungsten, to provide vertical connection between stacked up interconnect metal lines.
Term (Index) Definition
through silicon via, TSV,  vias etched through Si wafer to allow wafer-to-wafer interconnect scheme compatible with 3D wafer-level packaging.
Term (Index) Definition
via first,  in 3D packaging TSV is processed prior to wafer (chip) bonding.
via 7 hole etched in the interlayer dielectric which is then filled with metal, usually tungsten, to provide vertical connection between stacked up interconnect metal lines.
via last,  in 3D packaging TSV is processed after wafer (chip) thinning and bonding.
Term (Index) Definition
via last,  in 3D packaging TSV is processed after wafer (chip) thinning and bonding.
via 7 hole etched in the interlayer dielectric which is then filled with metal, usually tungsten, to provide vertical connection between stacked up interconnect metal lines.
via first,  in 3D packaging TSV is processed prior to wafer (chip) bonding.
Term (Index) Definition
via veil  residue resulting from the resist stripping process following via etch in multilevel interconnect scheme
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Created and operated by J. Ruzyllo. Copyright J. Ruzyllo 2001-2016. All rights reserved.

Information in this glossary is provided at the author's discretion. Any liability based on, or related to the contents of this glossary is disclaimed.