Semiconductor Glossary, Developed Semi OneSource.
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With over 2000 terms defined and explained, Semiconductor Glossary is the most complete reference in the field of semiconductors on the market today.












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Term (Index) Definition
trench  geometrical feature etched into semiconductor substrate; anisotropic etch in the direction normal to the surface; aspect ratio > 1.
anisotropic etch  etch in which etch rate in the direction normal to the surface is much higher than in direction parallel to the surface; no undercutting i.e. lateral distortion of pattern is minimized; needed to define very tight geometries.
trench isolation  deep narrow trench etched into the semiconductor substrate is filled with oxide; such trench is located in between adjacent devices in an integrated circuit to provide electrical isolation between them.
U-MOSFET, UMOS  power MOSFET with channel built into U-shaped trench etched into semiconductor substrate; extension of the VMOS concept; features lower than other power MOSFETs (DMOS, VMOS) on-resistance.
trench capacitor  capacitor built into the trench etched in the semiconductor substrate; by using trench configuration area of capacitor can be expanded (capacitance increased) without increasing area of the wafer needed to form the capacitor.
Term (Index) Definition
shallow trench isolation, STI  transistor isolation used in CMOS instead of LOCOS isolation.
Term (Index) Definition
trench capacitor  capacitor built into the trench etched in the semiconductor substrate; by using trench configuration area of capacitor can be expanded (capacitance increased) without increasing area of the wafer needed to form the capacitor.
storage capacitor  e.g. key element of a DRAM cell.
Term (Index) Definition
trench isolation  deep narrow trench etched into the semiconductor substrate is filled with oxide; such trench is located in between adjacent devices in an integrated circuit to provide electrical isolation between them.
LOCOS  Local Oxidation of Silicon; isolation scheme commonly used in MOS/CMOS silicon technology; thick (in the range of 500 nm) pad of thermally grown SiO2 separates adjacent devices (e.g. PMOS and NMOS transistor in CMOS structure); local oxidation is accomplished by using silicon nitride, Si3N4, to prevent oxidation of Si in selected areas, hence, "local" oxidation; prior to SiO2 pad formation silicon in between Si3N4 covered regions is implanted to form "channel stop"; Si3N4 mask is etched off following thermal oxidation and MOSFETs are ten formed in the open spaces.
shallow trench isolation, STI  transistor isolation used in CMOS instead of LOCOS isolation.
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