Semiconductor Glossary, Developed Semi OneSource.
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With over 2000 terms defined and explained, Semiconductor Glossary is the most complete reference in the field of semiconductors on the market today.












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Term (Index) Definition
latch up, latchup, latch-up  adverse effect occurring in CMOS devices; condition under which significant current flows through Si substrate between NMOS and PMOS parts of CMOS structure and degrades its performance; it occurs when under certain bias conditions two parasitic bipolar transistors resulting from CMOS configuration "latch" and provide high conductivity path between NMOS and PMOS parts of the device; various CMOS designs were conceived to prevent latch-up; implementation of CMOS technology on SOI substrates is an ultimate solution to the CMOS latch-up.
CMOS  Complementary Metal Oxide Semiconductor structure; consists of N-channel and P-channel MOS transistors; due to very low power consumption and dissipation as well minimization of the current in "off" state CMOS is a very effective device configuration for implementation of digital functions; CMOS is a key device in state-of-the-art silicon microelectronics.
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Information in this glossary is provided at the author's discretion. Any liability based on, or related to the contents of this glossary is disclaimed.