Semiconductor Glossary, Developed Semi OneSource.
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Term (Index) Definition
gate  structure used to control output current (i.e. flow of carriers in the channel) in the field effect transistor (FET); in MOSFET gate is comprised of gate contact and thin oxide; in MESFET gate is a Schottky contact; in JFET: metal and p-n junction.
drain  heavily doped region in semiconductor substrates located at the end of the channel in Field Effect Transistors; carriers are flowing out of the transistor through the drain.
Field Effect Transistor, FET  transistor in which output current (source-drain current)is controlled by the voltage applied to the gate which can be either an MOS structure (MOSFET), a p-n junction (JFET), or metal-semiconductor contact (MESFET); FET is an unipolar transistor, i.e. current is controlled by majority carriers only.
source  one of three terminals in Field Effect Transistors; a heavily doped region from which majority carriers are flowing into the channel.
Term (Index) Definition
double (dual) gate  innovative approach to MOSFET implementation; gate structure (gate oxide and gate contact)is formed on two sides of the channel, hence, "double"; doubles capacitance of the MOS gate without increasing device area; possible with new MOSFET's designs in which gate stack is normal to the surface; considered for next generation MOS-based switching devices (post-CMOS).
Term (Index) Definition
gate capacitance  for MOSFET/CMOS to operate properly MOS gate stack must feature certain minimum capacitance C~kA/d; as gate contact area A decreases due to scaling, thickness of gate dielectric d must decrease to maintain desired capacitance of the stack; when reduction of gate dielectric thickness is not possible due to the excessive tunneling current dielectric featuring dielectric constant k higher than SiOsub>2 must be used.
alternative dielectrics  dielectrics featuring dielectric constant k > 3.9 (3.9 is a dielectric constant of SiO2)and acting as gate oxides in silicon MOS devices instead of SiO2; referred to as "high-k dielectrics"; also dielectrics featuring dielectric constant k < 3.9 and used as ILD; referred to as "low-k dielectrics".
high-k dielectric  dielectric material featuring dielectric constant k higher than 3.9 which is k of SiO2; used as gate dielectric (amorphous) in MOS devices and in storage capacitors; high k increases capacitance, or keeps in unchanged at the reduced area of MOS gate and gate dielectric sufficiently thick to prevent excessive tunneling current.

Reference: See Semiconductor Notes for more information
tunneling, tunneling current  transport of electron across the potential barrier without changing its energy; as opposed to electron transport "over" the barrier (thermionic emission) in which case its energy is must be changed; tunneling probability is a strong function of the width ofpotential barrier; examples: tunneling across the potential barrier at the metal-semiconductor contact, or across the potential barrier at the p-n junction, or across an oxide (direct tunneling for oxide thinner than about 3 nm, Fowler-Nordheim tunneling for oxide 5-10 nm thick) in MOS structure.
Term (Index) Definition
gate contact  conducting material (metal, poly Si, or silicide) in the gate structure.
gate stack  gate metal (conductor)- gate oxide structure in a MOSFET/CMOS.
silicide, silicides  alloys of silicon and metals; contact materials in silicon device manufacturing; e.g. TiSi2, CoSi2, NiSi; combine advantageous features of metal contacts (e.g significantly lower resistivity than poly-Si) and poly-Si contacts(e.g. no electromigration).
poly - Si gate  polycrystalline Si gate commonly used as a gate contact in MOS/CMOS devices; used instead of metal gates because work function of poly-Si matches work function of Si substrate much closer than metals, hence, threshold voltage of transistor is significantly lower; also, poly Si is more resistant to temperature than, for instance, Al; drawback: in spite of being very heavily doped (and essentially acting as a conductor) poly-Si features resistivity two orders of magnitude higher than typical metals; moreover, poly-Si gets easily oxidized at the interface with gate oxide which is unacceptable in the case high-k dielectric is used as a gate oxide.
Term (Index) Definition
gate depletion,  occurs in silicon MOS gate stacks using high-k dielectric and poly Si gate contact; undesired formation of an ultra-thin oxide SiOx at the interface between high-k dielctric and poly Si gate contact; lowers capacitance of the gate stack; avoided by using metal gate contacts instead of poly Si.
Term (Index) Definition
gate dielectric  very thin layer of an insulator sandwiched between semiconductor and gate contact in MOS devices; in silicon technology it is typically a thermally grown SiO2, often nitrided; depending on application it can be as thin as 1.0-1.5 nm (advanced digital integrated circuits) and as thick as 50 nm (discrete power MOSFETs); in ultra-small geometry CMOS ICs SiO2 is replaced with insulators featuring higher than SiO2 dielectric constant; hafnium based dielectrics (oxide or silicate) are materials of choice in this case.
Term (Index) Definition
gate injection  during constant-current stress of MOS gate stacks electrons are injected into the oxide from the gate contact.
constant - current stress, CCS  technique used to study time dependent breakdown of gate oxide; constant current featuring predetermined density is injected into the oxide until it breaks down (gate voltage drops to zero).
substrate injection  during constant-current stress of MOS gate stacks electrons are injected into the oxide from the Si substrate.
Term (Index) Definition
gate length  effective length of the distance in the near-surface region of Si substrate between edges of the drain and source regions in the field effect transistor (including MOSFET and CMOS).
channel length  distance between source and drain in Field Effect Transistors; shorter the channel faster switching by the FET can be achieved; reduction of the channel length in MOSFETs is a driving force behind the progress in microelectronics.
Term (Index) Definition
gate oxidation,  process of thermal oxidation of silicon which forms an oxide for MOS gates; typically carried out in dry oxygen at the temperature determined by the desired thickness of the oxide.
gate oxide  a layer of very thin oxide sandwiched between semiconductor and gate contact in MOS devices; can be as thin as 1 nm in advance silicon digital integrated circuits and as thick as 70 nm in discrete power MOSFETs; typically thermally grown SiO2, often nitrided; in ultra-small geometry CMOS ICs SiO2 can be replaced with dielectrics fetauring higher than SiO2 dielectric constant.
Term (Index) Definition
gate oxide  a layer of very thin oxide sandwiched between semiconductor and gate contact in MOS devices; can be as thin as 1 nm in advance silicon digital integrated circuits and as thick as 70 nm in discrete power MOSFETs; typically thermally grown SiO2, often nitrided; in ultra-small geometry CMOS ICs SiO2 can be replaced with dielectrics fetauring higher than SiO2 dielectric constant.
high-k dielectric  dielectric material featuring dielectric constant k higher than 3.9 which is k of SiO2; used as gate dielectric (amorphous) in MOS devices and in storage capacitors; high k increases capacitance, or keeps in unchanged at the reduced area of MOS gate and gate dielectric sufficiently thick to prevent excessive tunneling current.

Reference: See Semiconductor Notes for more information
silicon dioxide, SiO2  silica; native oxide of silicon and at the same time an excellent insulator; the most common insulator in semiconductor device technology, particularly in silicon MOS/CMOS where it is use as a gate oxide; high quality films are obtained by thermal oxidation of silicon; thermal SiO2 forms smooth, low-defect interface with Si; can be also readily deposited by CVD; SiO2 performs various functions in silicon device technology which to large degree depends on outstanding characteristics of; also used in non-Si devices; Key parameters: energy gap Eg ~ 8eV, dielectric strength 5-15 x 106 V/cm depending on thickness, dielectric constant k = 3.9, density 2.3 g/cm3, refractive index n =1.46, melting point ~ 1700 oC; prone to contamination with alkali ions and sensitive to high energy radiation; in semiconductor technology used in the form amorphous thin films; single crystal SiO2 is known as quartz.
Term (Index) Definition
gate self-aligned process  key part of the MOS/CMOS fabrication sequence; gate stack (gate oxide and gate contact)is used as a mask during source and drain implantation, and hence, gate stack self-aligns with respect to source and drain regions.
Term (Index) Definition
gate stack  gate metal (conductor)- gate oxide structure in a MOSFET/CMOS.
Term (Index) Definition
metal MOS gate  for many years metals were not used as gate contact material in MOS/CMOS devices; instead, conducting poly-Si is used due to the work function matching work function of Si substrate (precondition for the low threshold voltage of an MOSFET); metal contacts are re-introduced to the mainstream CMOS technology at the time when high-k dielectrics are replacing SiO2 as a gate oxide in cutting edge CMOS technology(poly-Si forms an SiOx layer at the interface with gate dielectric; also Fermi level pinning may occur); different metals must be used as gate contacts in NMOS and PMOS part of the CMOS cell.
Term (Index) Definition
pi gate,   a 3D MOS gate which shape in cross-section resembles a Greek letter "pi".
Term (Index) Definition
poly - Si gate  polycrystalline Si gate commonly used as a gate contact in MOS/CMOS devices; used instead of metal gates because work function of poly-Si matches work function of Si substrate much closer than metals, hence, threshold voltage of transistor is significantly lower; also, poly Si is more resistant to temperature than, for instance, Al; drawback: in spite of being very heavily doped (and essentially acting as a conductor) poly-Si features resistivity two orders of magnitude higher than typical metals; moreover, poly-Si gets easily oxidized at the interface with gate oxide which is unacceptable in the case high-k dielectric is used as a gate oxide.
gate  structure used to control output current (i.e. flow of carriers in the channel) in the field effect transistor (FET); in MOSFET gate is comprised of gate contact and thin oxide; in MESFET gate is a Schottky contact; in JFET: metal and p-n junction.
gate contact  conducting material (metal, poly Si, or silicide) in the gate structure.
MOSFET  Metal-Oxide-Semiconductor Field Effect Transistor; FET with MOS structure as a gate; current flows in the channel between source and drain; channel is created by applying adequate potential to the gate contact and inverting semiconductor surface underneath the gate; MOSFET structure is implemented almost uniquely with Si and SiO2 gate oxide; efficient switching device which dominates logic and memory applications; PMOSFET (p-channel, n-type Si substrate) and NMOSFET (n-channel,p-type Si substrate) combined form basic CMOS cell.
Term (Index) Definition
retrograde gate  No Definition at the current time.
CMOS  Complementary Metal Oxide Semiconductor structure; consists of N-channel and P-channel MOS transistors; due to very low power consumption and dissipation as well minimization of the current in "off" state CMOS is a very effective device configuration for implementation of digital functions; CMOS is a key device in state-of-the-art silicon microelectronics.
retrograde well  an approach to well formation in CMOS structures; highest concentration of dopant (implanted) in the well is located at certain distance from the surface; denser, less susceptible to latch-up CMOS device result.
Term (Index) Definition
R-metal MOS gate   refractory metals (R-metals); e.g. W, Ta, Mo; considered for MOS gate applications due to the high resistance to temperature; as opposed to Al used as an MOS gate contact at that time; R-MOS process has never become a mainstream technology; poly-Si was used instead.
Term (Index) Definition
surround gate  gate in MOSFET/CMOS designed in such way that it surrounds channel; the goal is to increase gate contact area without increasing area of the entire CMOS cell.
double (dual) gate  innovative approach to MOSFET implementation; gate structure (gate oxide and gate contact)is formed on two sides of the channel, hence, "double"; doubles capacitance of the MOS gate without increasing device area; possible with new MOSFET's designs in which gate stack is normal to the surface; considered for next generation MOS-based switching devices (post-CMOS).
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