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Term (Index) Definition
drain  heavily doped region in semiconductor substrates located at the end of the channel in Field Effect Transistors; carriers are flowing out of the transistor through the drain.
drain engineering  modifications of the drain and channel region adjacent to the drain in integrated MOS and CMOS devices; goal is to improve characteristics of MOS transistors with ultra-short channel.
Field Effect Transistor, FET  transistor in which output current (source-drain current)is controlled by the voltage applied to the gate which can be either an MOS structure (MOSFET), a p-n junction (JFET), or metal-semiconductor contact (MESFET); FET is an unipolar transistor, i.e. current is controlled by majority carriers only.
gate  structure used to control output current (i.e. flow of carriers in the channel) in the field effect transistor (FET); in MOSFET gate is comprised of gate contact and thin oxide; in MESFET gate is a Schottky contact; in JFET: metal and p-n junction.
LDD  Lightly Doped Drain; part of the drain engineering strategy in advanced CMOS; designed to minimize hot-carrier effects; the reduced doping gradient between drain and channel lowers electric field in the channel in the vicinity of the drain; implementation: moderate implant before spacer formation, heavy implant after spacer formation.
source  one of three terminals in Field Effect Transistors; a heavily doped region from which majority carriers are flowing into the channel.
LATID  Large-Angle-Tilt Implanted Drain; part of the "drain engineering" strategy in ultra-small geometry CMOS.
Term (Index) Definition
drain engineering  modifications of the drain and channel region adjacent to the drain in integrated MOS and CMOS devices; goal is to improve characteristics of MOS transistors with ultra-short channel.
raised source-drain  feature of the advanced CMOS/MOSFET design; source and drain regions are raised (additional layer of Si is deposited epitaxially)with respect to the plane of the gate oxide-Si substrate interface to improve device performance.
Term (Index) Definition
drain extension  low doping extension of source and drain toward channel; carried out by ion implantation; used in advanced CMOS to prevent premature breakdown of drain-substrate junction.
drain engineering  modifications of the drain and channel region adjacent to the drain in integrated MOS and CMOS devices; goal is to improve characteristics of MOS transistors with ultra-short channel.
Term (Index) Definition
elevated drain  drain region in MOSFET/CMOS is extended above the surface of the wafer by means of selective epitaxy; needed in ultra-short channel MOSFETs where drain region must beextremely shallow (as thin as about 30 nm); e.g. in ultra-thin SOI CMOS devices; same concept as raised drain.
drain  heavily doped region in semiconductor substrates located at the end of the channel in Field Effect Transistors; carriers are flowing out of the transistor through the drain.
drain engineering  modifications of the drain and channel region adjacent to the drain in integrated MOS and CMOS devices; goal is to improve characteristics of MOS transistors with ultra-short channel.
elevated source  source region in MOSFET/CMOS is extended above the surface of the wafer by means of selective epitaxy; needed in ultra-short channel MOSFETs where source region must be extremely shallow (less than about 30 nm); e.g. in ultra-thin SOI CMOS devices.
Term (Index) Definition
elevated drain  drain region in MOSFET/CMOS is extended above the surface of the wafer by means of selective epitaxy; needed in ultra-short channel MOSFETs where drain region must be extremely shallow (less than about 30 nm); e.g. in ultra-thin SOI CMOS devices.
drain  heavily doped region in semiconductor substrates located at the end of the channel in Field Effect Transistors; carriers are flowing out of the transistor through the drain.
drain engineering  modifications of the drain and channel region adjacent to the drain in integrated MOS and CMOS devices; goal is to improve characteristics of MOS transistors with ultra-short channel.
elevated source  source region in MOSFET/CMOS is extended above the surface of the wafer by means of selective epitaxy; needed in ultra-short channel MOSFETs where source region must be extremely shallow (less than about 30 nm); e.g. in ultra-thin SOI CMOS devices.
Term (Index) Definition
lightly doped drain, LDD  reduced doping of the drain region in veru small geometry MOS/CMOS transistor; part of the drain engineering strategy in advanced CMOS; designed to control drain-substarte breakdown; the reduced doping gradient between drain and channel lowers electric field in the channel in the vicinity of the drain; implementation: moderate implant before spacer formation, heavy implant after spacer formation.
drain  heavily doped region in semiconductor substrates located at the end of the channel in Field Effect Transistors; carriers are flowing out of the transistor through the drain.
drain engineering  modifications of the drain and channel region adjacent to the drain in integrated MOS and CMOS devices; goal is to improve characteristics of MOS transistors with ultra-short channel.
drain extension  low doping extension of source and drain toward channel; carried out by ion implantation; used in advanced CMOS to prevent premature breakdown of drain-substrate junction.
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Jerzy Ruzyllo is a Distinguished Professor Emeritus in the Department of Electrical Engineering at Penn State University.



This book gives a complete account of semiconductor engineering covering semiconductor properties, semiconductor materials, semiconductor devices and their uses, process technology, fabrication processes, and semiconductor materials and process characterization.


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Created and operated by J. Ruzyllo. Copyright © J. Ruzyllo 2001-2016. All rights reserved.

Information in this glossary is provided at the author's discretion. Any liability based on, or related to the contents of this glossary is disclaimed.