Semiconductor Glossary, Developed Semi OneSource.

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With over 2000 terms defined and explained, Semiconductor Glossary is the most complete reference in the field of semiconductors on the market today.

Including some 500 new terms defined and remaining terms updated and modified, a 2nd edition book version of this glossary is now available.

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Term (Index) Definition
channel stop  p+ implanted layer underneath oxide pad in LOCOS isolation scheme in CMOS devices; put in place to prevent formation of an inversion layer which would create a conductive channel between PMOS and NMOS parts of the CMOS cell.
latch up, latchup, latch-up  adverse effect occurring in CMOS devices; condition under which significant current flows through Si substrate between NMOS and PMOS parts of CMOS structure and degrades its performance; it occurs when under certain bias conditions two parasitic bipolar transistors resulting from CMOS configuration "latch" and provide high conductivity path between NMOS and PMOS parts of the device; various CMOS designs were conceived to prevent latch-up; implementation of CMOS technology on SOI substrates is an ultimate solution to the CMOS latch-up.
LOCOS  Local Oxidation of Silicon; isolation scheme commonly used in MOS/CMOS silicon technology; thick (in the range of 500 nm) pad of thermally grown SiO2 separates adjacent devices (e.g. PMOS and NMOS transistor in CMOS structure); local oxidation is accomplished by using silicon nitride, Si3N4, to prevent oxidation of Si in selected areas, hence, "local" oxidation; prior to SiO2 pad formation silicon in between Si3N4 covered regions is implanted to form "channel stop"; Si3N4 mask is etched off following thermal oxidation and MOSFETs are ten formed in the open spaces.
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Information in this glossary is provided at the author's discretion. Any liability based on, or related to the contents of this glossary is disclaimed.