Semiconductor OneSource: Semiconductor Glossary -- Search For : channel stop

Term (Index)	Definition
channel stop	p⁺ implanted layer underneath oxide pad in LOCOS isolation scheme in CMOS devices; put in place to prevent formation of an inversion layer which would create a conductive channel between PMOS and NMOS parts of the CMOS cell.
latch up, latchup, latch-up	adverse effect occurring in CMOS devices; condition under which significant current flows through Si substrate between NMOS and PMOS parts of CMOS structure and degrades its performance; it occurs when under certain bias conditions two parasitic bipolar transistors resulting from CMOS configuration "latch" and provide high conductivity path between NMOS and PMOS parts of the device; various CMOS designs were conceived to prevent latch-up; implementation of CMOS technology on SOI substrates is an ultimate solution to the CMOS latch-up.
LOCOS	Local Oxidation of Silicon; isolation scheme commonly used in MOS/CMOS silicon technology; thick (in the range of 500 nm) pad of thermally grown SiO₂ separates adjacent devices (e.g. PMOS and NMOS transistor in CMOS structure); local oxidation is accomplished by using silicon nitride, Si₃N₄, to prevent oxidation of Si in selected areas, hence, "local" oxidation; prior to SiO₂ pad formation silicon in between Si₃N₄ covered regions is implanted to form "channel stop"; Si₃N₄ mask is etched off following thermal oxidation and MOSFETs are ten formed in the open spaces.