Semiconductor OneSource: Semiconductor Glossary -- Search For : channel

Term (Index)	Definition
channel	high conductivity region connecting source and drain in Field Effect Transistors; conductivity of channel is controlled by a gate voltage; depending on the gate voltage channel conductivity can be very high (channel "closed" or very high (channel "open"; by turning channel "on" and "off" switching in FETs is accomplished.
Field Effect Transistor, FET	transistor in which output current (source-drain current)is controlled by the voltage applied to the gate which can be either an MOS structure (MOSFET), a p-n junction (JFET), or metal-semiconductor contact (MESFET); FET is an unipolar transistor, i.e. current is controlled by majority carriers only.

Term (Index)	Definition
channel length	distance between source and drain in Field Effect Transistors; shorter the channel faster switching by the FET can be achieved; reduction of the channel length in MOSFETs is a driving force behind the progress in microelectronics.
CMOS	Complementary Metal Oxide Semiconductor structure; consists of N-channel and P-channel MOS transistors; due to very low power consumption and dissipation as well minimization of the current in "off" state CMOS is a very effective device configuration for implementation of digital functions; CMOS is a key device in state-of-the-art silicon microelectronics.
MOSFET	Metal-Oxide-Semiconductor Field Effect Transistor; FET with MOS structure as a gate; current flows in the channel between source and drain; channel is created by applying adequate potential to the gate contact and inverting semiconductor surface underneath the gate; MOSFET structure is implemented almost uniquely with Si and SiO₂ gate oxide; efficient switching device which dominates logic and memory applications; PMOSFET (p-channel, n-type Si substrate) and NMOSFET (n-channel,p-type Si substrate) combined form basic CMOS cell.

Term (Index)	Definition
channel stop	p⁺ implanted layer underneath oxide pad in LOCOS isolation scheme in CMOS devices; put in place to prevent formation of an inversion layer which would create a conductive channel between PMOS and NMOS parts of the CMOS cell.
latch up, latchup, latch-up	adverse effect occurring in CMOS devices; condition under which significant current flows through Si substrate between NMOS and PMOS parts of CMOS structure and degrades its performance; it occurs when under certain bias conditions two parasitic bipolar transistors resulting from CMOS configuration "latch" and provide high conductivity path between NMOS and PMOS parts of the device; various CMOS designs were conceived to prevent latch-up; implementation of CMOS technology on SOI substrates is an ultimate solution to the CMOS latch-up.
LOCOS	Local Oxidation of Silicon; isolation scheme commonly used in MOS/CMOS silicon technology; thick (in the range of 500 nm) pad of thermally grown SiO₂ separates adjacent devices (e.g. PMOS and NMOS transistor in CMOS structure); local oxidation is accomplished by using silicon nitride, Si₃N₄, to prevent oxidation of Si in selected areas, hence, "local" oxidation; prior to SiO₂ pad formation silicon in between Si₃N₄ covered regions is implanted to form "channel stop"; Si₃N₄ mask is etched off following thermal oxidation and MOSFETs are ten formed in the open spaces.

Term (Index)	Definition
vertical channel	channel in MOSFETs that is normal to the wafer surface; vertical channel is better compatible with high power handling capabilities than lateral channel configuration; implemented in VMOS, DMOS, and UMOS FETs.
U-MOSFET, UMOS	power MOSFET with channel built into U-shaped trench etched into semiconductor substrate; extension of the VMOS concept; features lower than other power MOSFETs (DMOS, VMOS) on-resistance.