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Term (Index) Definition
MOSFET  Metal-Oxide-Semiconductor Field Effect Transistor; FET with MOS structure as a gate; current flows in the channel between source and drain; channel is created by applying adequate potential to the gate contact and inverting semiconductor surface underneath the gate; MOSFET structure is implemented almost uniquely with Si and SiO2 gate oxide; efficient switching device which dominates logic and memory applications; PMOSFET (p-channel, n-type Si substrate) and NMOSFET (n-channel,p-type Si substrate) combined form basic CMOS cell.
JFET  Junction Field Effect Transistor; field effect transistor in which channel and its conductivity is controlled by changing width of the space charge region associated with a p-n junction.
MESFET  Metal Semiconductor Field Effect Transistor; FET with metal-semiconductor contact (Schottky diode) as a gate; allows implementation of field effect transistor with semiconductors which do not have high quality native oxide (e.g. GaAs), and hence, are not compatible with MOS gate approach.
Term (Index) Definition
depletion mode MOSFET  normally "on" MOSFET; i.e. device in which gate voltage must be applied to turn it off; in other words channel exists even at VG=0.
Term (Index) Definition
enhancement mode MOSFET  normally "off" MOSFET; i.e. device in which gate voltage must be applied to turn it on; in other words channel does not exist at VG=0.
depletion mode MOSFET  normally "on" MOSFET; i.e. device in which gate voltage must be applied to turn it off; in other words channel exists even at VG=0.
Term (Index) Definition
MOSFET scaling,  reduction of MOSFET's geometry for the purpose of improving its performance; the goal is to reduce channel (gate) length and in the process maintain device fully operational; scalng rules must be followed to avoid undesired short-channel effects.
scaling rules  design rules which must be followed while scaling down geometry of integrated devices and interconnect lines; arbitrary reduction of key geometries, e.g. channel length in MOSFETs, may results in dysfunctional devices, e.g. short-channel effects in MOSFET.
Term (Index) Definition
normally "off" MOSFET  enhancement mode MOSFET; i.e. device in which gate voltage must be applied to turn the device on; in other words channel does not exist at VG = 0.
Term (Index) Definition
normally "on" MOSFET  depletion mode MOSFET; i.e. device in which gate voltage must be applied to turn it off; in other words channel exists even at VG=0.
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Jerzy Ruzyllo is a Distinguished Professor Emeritus in the Department of Electrical Engineering at Penn State University.



This book gives a complete account of semiconductor engineering covering semiconductor properties, semiconductor materials, semiconductor devices and their uses, process technology, fabrication processes, and semiconductor materials and process characterization.


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Created and operated by J. Ruzyllo. Copyright © J. Ruzyllo 2001-2016. All rights reserved.

Information in this glossary is provided at the author's discretion. Any liability based on, or related to the contents of this glossary is disclaimed.