Semiconductor Glossary, Developed Semi OneSource.

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With over 2000 terms defined and explained, Semiconductor Glossary is the most complete reference in the field of semiconductors on the market today.

Including some 500 new terms defined and remaining terms updated and modified, a 2nd edition book version of this glossary is now available.

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Term (Index) Definition
First 45 nm transistor  Intel's transistor which uses 45 nm technology and which employs high-k gate dielectric and metal gate contacts to push transistor performance to unprecedented levels (e.g. 20 % improvement in transistor switching speed as compared to 65 nm technology)

Reference: First 45 nm transistor
gate contact  conducting material (metal, poly Si, or silicide) in the gate structure.
gate dielectric  very thin layer of an insulator sandwiched between semiconductor and gate contact in MOS devices; in silicon technology it is typically a thermally grown SiO2, often nitrided; depending on application it can be as thin as 1.0-1.5 nm (advanced digital integrated circuits) and as thick as 50 nm (discrete power MOSFETs); in ultra-small geometry CMOS ICs SiO2 is replaced with insulators featuring higher than SiO2 dielectric constant; hafnium based dielectrics (oxide or silicate) are materials of choice in this case.
high-k dielectric  dielectric material featuring dielectric constant k higher than 3.9 which is k of SiO2; used as gate dielectric (amorphous) in MOS devices and in storage capacitors; high k increases capacitance, or keeps in unchanged at the reduced area of MOS gate and gate dielectric sufficiently thick to prevent excessive tunneling current.

Reference: See Semiconductor Notes for more information
metal MOS gate  for many years metals were not used as gate contact material in MOS/CMOS devices; instead, conducting poly-Si is used due to the work function matching work function of Si substrate (precondition for the low threshold voltage of an MOSFET); metal contacts are re-introduced to the mainstream CMOS technology at the time when high-k dielectrics are replacing SiO2 as a gate oxide in cutting edge CMOS technology(poly-Si forms an SiOx layer at the interface with gate dielectric; also Fermi level pinning may occur); different metals must be used as gate contacts in NMOS and PMOS part of the CMOS cell.
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Created and operated by J. Ruzyllo. Copyright J. Ruzyllo 2001-2016. All rights reserved.

Information in this glossary is provided at the author's discretion. Any liability based on, or related to the contents of this glossary is disclaimed.