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Sunday, May 31, 2015

#326 Charge carrier scattering depends on material

Even more significantly than the crystallographic defects (see blog #324 and #325) the very nature of interatomic bonding will affect scattering of charge carriers, and hence, their mobility in any given material.


For instance, in the case of inorganic covalently-bonded semiconductors charge carriers are moving with an electric filed as highly delocalized plane waves in wide bands and a  high electron mobility in the range ~103 cm2V-1s-1results. In the case of organic semiconductors featuring very weak intermolecular forces, electrons are hopping between localized states and are subject to scattering at every stop. The resulting electron mobility is in the range of the mere ~1 cm2V-1s-1.

Posted by Jerzy Ruzyllo at 10:11 AM | Semiconductors | Link

Sunday, May 3, 2015

#325 Charge carrier scattering depends on crystal structure

For all practical purposes defects scattering (see #324) comes to play in the major way only in the single crystal semiconductors, i.e. in those featuring a long-range periodic order of the crystal lattice throughout the entire piece of material.



In the polycrystalline version of the same semiconductor, e.g. silicon, Si, where a long-range periodic order is maintained only within limited in volume grains, defects related to the grain boundaries will inherently cause major scattering of the moving carriers and thus, decrease significantly charge carrier mobility.



Finally, the same silicon comes also in the non-crystalline (amorphous) thin-film version where there is no long-range periodic order. At the very high density of point defects in amorphous thin-film silicon the carrier mobility decreases by up to three orders of magnitude as compared to single-crystal bulk silicon. That is not to say that becasue of the dismal mobility charactersitics amporphous semiconductors are not useful in practical device applications. Just consider a broad field of thin-film transistor (TFT) technology....


Posted by Jerzy Ruzyllo at 08:55 PM | Semiconductors | Link

Sunday, April 19, 2015

#324 Surface defects and carrier scattering

As  pointed out in the previous blog (#323), defect scattering is a main reason for the much reduced charge carrier mobility at the surface of a crystalline semiconductor  as compared to its bulk. Among crystal defects, wchich include point defects, line defects, planar defects and volume defects, the point defects are primarily responsiblefor this effect.



Point defects are the highly localized imperfections of a crystalline structure which affect the periodicity of the crystal mostly in, or around, one unit cell. Whether it is a missing atom (vacancy) or or interstitially located additional atom, the effect on the moving carriers will be pronounced. What is making the surface particularly effective in disrupting the flow of charge carriers is the fact that it represents an abrupt  discontinuity of the lattice with broken interatomic bonds (“dangling” bonds) and missing atoms all of which act as the scattering centers.


Posted by Jerzy Ruzyllo at 08:32 AM | Semiconductors | Link

Sunday, April 5, 2015

#323 Scattering

The electrons and holes moving in semiconductor under the influence of an electric field are subject to inevitable collisions causing their scattering and adversely altering their transport across the lattice. The difference in the extent and the nature of scattering in the bulk of semiconductor (see previous entry) and in its near-surface region is a cause of the fundamental difference in the conductivity of semiconductor in these two regions.



One can envision the lattice scattering (a result of interactions between the electrons and holes in motion and the vibrating lattice atoms) and ionized dopant scattering (a result of interactions between the electrons and holes and the dopant ions located  in the lattice) being somewhat different in the bulk of semiconductor and at its surface. It is, however, the defect scattering (a result of interactions between the electrons and holes in motion and the defects in the atomic structure of semiconductor) that accounts for the key differences between carrier transport in the bulk and in the near-surface region. As mentioned in the previous entry this difference manifests itself in the significantly reduced carrier mobility in the latter case.


Posted by Jerzy Ruzyllo at 07:55 PM | Semiconductors | Link

Sunday, March 15, 2015

#322 How relevant is the concept of "bulk" semiconductor?

The term “bulk” applies to the part of semiconductor in which the periodic potential associated with the atomic structure is assumed to be infinite in all three dimensions. All the key electronic properties of semiconductors, such as for instance carrier mobility, are commonly defined for the bulk portion of the semiconductor material.


The problem is that in the vast majority of the current semiconductor devices the concept of bulk is essentially irrelevant. Whether it is a transistor in logic ICs or a laser diode or a thin-film solar cell the assumption of the infinite periodicity of the potential is invalid. It is simply because films are so thin that the concept of bulk does not apply to the volume of material between its surface at one end and the interface with the other material at the other.



In such material configurations, physical properties of semiconductor, charge carrier transport in particular, are controlled entirely by the surface and near-surface  phenomena and are very different from those defined for the bulk of the same material. For instance, the mobility of electrons in the bulk of silicon (at room temperature) is about 1,500 cm2/Vsec. However, the same mobility of electrons in the strongly confined channel of the Si transistor is typically four or more times smaller which resluts in the propoetionally reduce electrical conductivity of semiconductor.


Posted by Jerzy Ruzyllo at 08:01 AM | Semiconductors | Link

Sunday, March 1, 2015

#321 Atomic-scale and its intricacies

The atomic-scale technology opens new possibilities in semiconductor device engineering and this is great. But with a caveat, however. Problem is that electrons start behaving in a strange way in the extremely confined spaces. Whether it is in the heavily 2D confined planar channel in Ultra-Thin Body SOI or vertical “fin” acting as a channel, current carrying electrons are subject to interactions which they do not encounter in 3D, or bulk, materials and which result in the deterioration of device performance.



What is the threshold at which those undesired effects are coming to play? It depends on the electric field which is moving electrons, crystal structure of the material and most notably on the crystallographic orientation of the surfaces confining the space in which electrons are moving. It appears that at the thickness/width somewhere around 4-5nm electrons “discomfort” is becoming very noticeable.  It means that when the semiconductor is confined in one dimension to less than about 20 atoms across (becoming effectively a 2D material system) there is no room for electrons to drift across it in the unobstructed way. They start interacting with each other and encounter scattering events which cause significant reduction of their mobility, and hence, deterioration of current driving characteristics of the transistor.


The good news is that it does not mean the end of the story for the atomic-scale technology. It only means that the description of the electrons behavior in semiconductors using tools of the classical physics runs its course and we need to switch to the next gear and adopt the laws of the quantum physics to comprehend what is going on. In other words, we need to forget about the corpuscular nature of an electron and consider it as a wave. Simple, right?

Posted by Jerzy Ruzyllo at 05:26 PM | Semiconductors | Link

Sunday, February 22, 2015

#320 Atomic-scale technology - horizontally!

What is even more impressive than the atomic-scale manipulation of vertical dimensions (see previous blog) is our ability to manipulate semiconductors and other solids  and to create horizontal atomic-scale geometries.


While in the vertical manipulations atom-by-atom deposition is relatively easy to implement these days, definition of horizontal nano-geaometries depends entirely on the resolution of the lithographic processes and precision of the follow up etching processes. In spite of the all so well recognized lithography resolution's related challenges, atomic-scale definition of the horizontal features is the reality.


Just consider for instance less than 10 nm wide "fins" formed on the wafer surface during the FinFET fabrication. Based on the numbers considered in the previous blog, a 5 nm "fin" is an about 20 atoms wide. In top-down processes it is a combination of the resolution of the lithographic process and precision of subsequent etching process that makes it possible.


Posted by Jerzy Ruzyllo at 05:36 PM | Semiconductors | Link

Sunday, February 8, 2015

#319 Atomic-scale technology

Assigning physical dimension to an atom is a tricky proposition. Still, adopting some simplifications, radius of the atoms of elements in the periodic table of elements can be defined both empirically as well through calculations.


Recognizing adopted short cuts, we can assume for the purpose of this discussion that the size of the silicon atom is about 250 picometers or using more familiar unit of length about 0.25 nanometer.


Consider now that the semiconductor films thinner than 10 nm are readily available by means of Molecular Beam Epitaxy (MBE) and the thickness of MOSFET’s channel in ultra-thin body SOI can be controlled down to single nanometers which means that it can be made in the controlled fashion less than 20 atoms thick. Add to it one atom thick graphene which we have learned to form and manipulate pretty effectively and the term "atomic-scale technology" rather than "nanotechnology" seems to more adequately reflect state-of-the-art in semiconductor technology these days.


Posted by Jerzy Ruzyllo at 03:52 PM | Semiconductors | Link

Sunday, January 25, 2015

#318 14th Semiconductor cleaning symposium

This is to let you know that the 14th International Symposium on Semiconductor Cleaning Science and Technology (SCST 14) will be as usual organized under the auspices of ECS this time in Phoenix, AZ, Oct. 11-16, 2015. See the Call for Papers , consider submitting an abstratct by May 1, 2015 and coming to Phoenix to enjoy a very fine conference.

Posted by Jerzy Ruzyllo at 03:16 PM | Semiconductors | Link

Sunday, January 11, 2015

#317 "3.9" is an another number to remember.

Following on the "number to remember" theme, 3.9 is another number which is flat out remembered by those involved in semiconductor engineering.


The dielectric constant k of SiO2 is 3.9. What is special about this value is that it serves as a reference in defining what is a high-k dielectric and what is a low-k dielectric. In the broadly commonly accepted terminology the dielectrics featuring k>3.9 are referred to as high-k dielectrics and those featuring k < 3.9 as low-k dielectrics.
The high-k dielectrics are needed wherever strong capacitive coupling between two conductors separated by  the dielectric is needed. The most obvious example is a MOS gate stack where, since 45 nm technology generation, gate dielectrics featuring high-k are used so that adequate gate capacitance is maintined at the physically thicker dielectric.
The  demand for the low-k dielectrics is coming from the multi-level interconnect technology where the capacitive coupling between two interconnect lines is highly undesirable, and hence,  interlayer dielectrics featuring as low as possible dielectric constant must be used.


In the light of the key role both high-k and low-k dielectrics are playing, a "3.9" has become a number of great relevance in the advanced semiconductor engineering.  I found it interesting that some 15-20 years ago the issue of high- and low-k was not of much relevance in semiconductor device engineering  as  SiO2 with its  k= 3.9 was used in both MOS gates and multilevel metallization applications.


Posted by Jerzy Ruzyllo at 04:50 PM | Semiconductors | Link

‹‹ ›› is the personal blog of Jerzy Ruzyllo. With over 35 years of experience in academic research and teaching in the area of semiconductor engineering (currently holding position of a Distinguished Professor of Electrical Engineering and Professor of Materials Science and Engineering at Penn State University), he has a unique perspective on the developments in this progress driving technical domain and enjoys blogging about it.

With over 2000 terms defined and explained, Semiconductor Glossary is the most complete reference in the field of semiconductors on the market today.

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