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Sunday, August 16, 2015

#329 Silicon vs. sapphire - an interesting competition

Whether it is a monolithic integrated circuit, light-emitting diode or a silicon carbide power transistor the semiconductor circuitry or a discreet device requires a substrate upon which it is formed. The substrates used in semiconductor device manufacturing were frequently a topic of my past blogs (see e.g. blogs #222 and #236).  


Because of the availability of the very large ( up to 450 mm in diameter), high quality (essentially defect-free), reasonably priced Si wafers there is no problem with the substrates in the case of any single-crystal Si based electronic circuits and devices.

Situation is very different, however, when it comes to the devices formed using semiconductor materials which do not have their native, high quality, large and relatively low-cost substrate wafers. In such cases sapphire is quite commonly  a substrate of choice (see e.g. blogs #17 and #222).  The best example is here a common use of sapphire as a substrate for GaN in the manufacture of LEDs for lighting applications.


For various reasons, related not only to the cost, but also to some other characteristics coming to play in the specific device applications, silicon would be a desirable substrate for a range of III-V compound semiconductors (see e.g. blog #231) including GaN (see blog #167).


According to the recent research reports, significant progress in heteroepitaxial deposition of GaN on the Si substrate is being accomplished.


What the above seems to suggest is that an interesting "competition" between  silicon and sapphire substrate wafers for the lead role in the heteroepitaxial device applications is shaping up. It looks like an old, good silicon may once again show its strenghts...



Posted by Jerzy Ruzyllo at 12:22 PM | Semiconductors | Link

Tuesday, July 21, 2015

#328 14th ECS Semiconductor Cleaning Symposium

If you are interested in the key area of semiconductor cleaning and surface engineering you need to know this:


The 14th International Symposium on Semiconductor Cleaning Science and Technology will be held during the ECS Fall Meeting in Phoenix, AZ, Oct. 11-15, 2015 (see a complete symposium program). 


Hope to see you there….


Posted by Jerzy Ruzyllo at 11:24 AM | Semiconductors | Link

Sunday, June 7, 2015

#327 Electron transport in graphene

Starting with blogs # 30 and #34 from some 7.5 years ago (yes, time is flying!), I devoted several entries to this “marvel material”. This time, in the spirit of the last three blogs, it is about the electron transport in graphene.The topic is hot as in theory electron mobility in graphene can be as high as some 200,000 cm2V-1s-1 (for comparison, electron mobility in bulk silicon is a mere 1,500  cm2V-1s-1 at room temperature).



The problem is that such high electron mobility is possible only in the free-standing or otherwise somehow suspended graphene. As soon as graphene comes in contact with other materials (e.g. SiC or metals on the surfaces of which it is formed) the electrons  moving in graphene are subject to a severe scattering and their mobility drops by amost two orders of magnitude.



It is abvious that  the making of the working, mass-manufactured transistors using a free-standing or suspended one-atom thick sheet of carbon is going to create truly major manufacturability related  challenges. It will be interesting to follow a progress in this regard. A usefulness of graphene in transistor applications will depend on it


Posted by Jerzy Ruzyllo at 05:28 PM | Semiconductors | Link

Sunday, May 31, 2015

#326 Charge carrier scattering depends on material

Even more significantly than the crystallographic defects (see blog #324 and #325) the very nature of interatomic bonding will affect scattering of charge carriers, and hence, their mobility in any given material.


For instance, in the case of inorganic covalently-bonded semiconductors charge carriers are moving with an electric filed as highly delocalized plane waves in wide bands and a  high electron mobility in the range ~103 cm2V-1s-1results. In the case of organic semiconductors featuring very weak intermolecular forces, electrons are hopping between localized states and are subject to scattering at every stop. The resulting electron mobility is in the range of the mere ~1 cm2V-1s-1.

Posted by Jerzy Ruzyllo at 10:11 AM | Semiconductors | Link

Sunday, May 3, 2015

#325 Charge carrier scattering depends on crystal structure

For all practical purposes defects scattering (see #324) comes to play in the major way only in the single crystal semiconductors, i.e. in those featuring a long-range periodic order of the crystal lattice throughout the entire piece of material.



In the polycrystalline version of the same semiconductor, e.g. silicon, Si, where a long-range periodic order is maintained only within limited in volume grains, defects related to the grain boundaries will inherently cause major scattering of the moving carriers and thus, decrease significantly charge carrier mobility.



Finally, the same silicon comes also in the non-crystalline (amorphous) thin-film version where there is no long-range periodic order. At the very high density of point defects in amorphous thin-film silicon the carrier mobility decreases by up to three orders of magnitude as compared to single-crystal bulk silicon. That is not to say that becasue of the dismal mobility charactersitics amporphous semiconductors are not useful in practical device applications. Just consider a broad field of thin-film transistor (TFT) technology....


Posted by Jerzy Ruzyllo at 08:55 PM | Semiconductors | Link

Sunday, April 19, 2015

#324 Surface defects and carrier scattering

As  pointed out in the previous blog (#323), defect scattering is a main reason for the much reduced charge carrier mobility at the surface of a crystalline semiconductor  as compared to its bulk. Among crystal defects, wchich include point defects, line defects, planar defects and volume defects, the point defects are primarily responsiblefor this effect.



Point defects are the highly localized imperfections of a crystalline structure which affect the periodicity of the crystal mostly in, or around, one unit cell. Whether it is a missing atom (vacancy) or or interstitially located additional atom, the effect on the moving carriers will be pronounced. What is making the surface particularly effective in disrupting the flow of charge carriers is the fact that it represents an abrupt  discontinuity of the lattice with broken interatomic bonds (“dangling” bonds) and missing atoms all of which act as the scattering centers.


Posted by Jerzy Ruzyllo at 08:32 AM | Semiconductors | Link

Sunday, April 5, 2015

#323 Scattering

The electrons and holes moving in semiconductor under the influence of an electric field are subject to inevitable collisions causing their scattering and adversely altering their transport across the lattice. The difference in the extent and the nature of scattering in the bulk of semiconductor (see previous entry) and in its near-surface region is a cause of the fundamental difference in the conductivity of semiconductor in these two regions.



One can envision the lattice scattering (a result of interactions between the electrons and holes in motion and the vibrating lattice atoms) and ionized dopant scattering (a result of interactions between the electrons and holes and the dopant ions located  in the lattice) being somewhat different in the bulk of semiconductor and at its surface. It is, however, the defect scattering (a result of interactions between the electrons and holes in motion and the defects in the atomic structure of semiconductor) that accounts for the key differences between carrier transport in the bulk and in the near-surface region. As mentioned in the previous entry this difference manifests itself in the significantly reduced carrier mobility in the latter case.


Posted by Jerzy Ruzyllo at 07:55 PM | Semiconductors | Link

Sunday, March 15, 2015

#322 How relevant is the concept of "bulk" semiconductor?

The term “bulk” applies to the part of semiconductor in which the periodic potential associated with the atomic structure is assumed to be infinite in all three dimensions. All the key electronic properties of semiconductors, such as for instance carrier mobility, are commonly defined for the bulk portion of the semiconductor material.


The problem is that in the vast majority of the current semiconductor devices the concept of bulk is essentially irrelevant. Whether it is a transistor in logic ICs or a laser diode or a thin-film solar cell the assumption of the infinite periodicity of the potential is invalid. It is simply because films are so thin that the concept of bulk does not apply to the volume of material between its surface at one end and the interface with the other material at the other.



In such material configurations, physical properties of semiconductor, charge carrier transport in particular, are controlled entirely by the surface and near-surface  phenomena and are very different from those defined for the bulk of the same material. For instance, the mobility of electrons in the bulk of silicon (at room temperature) is about 1,500 cm2/Vsec. However, the same mobility of electrons in the strongly confined channel of the Si transistor is typically four or more times smaller which resluts in the propoetionally reduce electrical conductivity of semiconductor.


Posted by Jerzy Ruzyllo at 08:01 AM | Semiconductors | Link

Sunday, March 1, 2015

#321 Atomic-scale and its intricacies

The atomic-scale technology opens new possibilities in semiconductor device engineering and this is great. But with a caveat, however. Problem is that electrons start behaving in a strange way in the extremely confined spaces. Whether it is in the heavily 2D confined planar channel in Ultra-Thin Body SOI or vertical “fin” acting as a channel, current carrying electrons are subject to interactions which they do not encounter in 3D, or bulk, materials and which result in the deterioration of device performance.



What is the threshold at which those undesired effects are coming to play? It depends on the electric field which is moving electrons, crystal structure of the material and most notably on the crystallographic orientation of the surfaces confining the space in which electrons are moving. It appears that at the thickness/width somewhere around 4-5nm electrons “discomfort” is becoming very noticeable.  It means that when the semiconductor is confined in one dimension to less than about 20 atoms across (becoming effectively a 2D material system) there is no room for electrons to drift across it in the unobstructed way. They start interacting with each other and encounter scattering events which cause significant reduction of their mobility, and hence, deterioration of current driving characteristics of the transistor.


The good news is that it does not mean the end of the story for the atomic-scale technology. It only means that the description of the electrons behavior in semiconductors using tools of the classical physics runs its course and we need to switch to the next gear and adopt the laws of the quantum physics to comprehend what is going on. In other words, we need to forget about the corpuscular nature of an electron and consider it as a wave. Simple, right?

Posted by Jerzy Ruzyllo at 05:26 PM | Semiconductors | Link

Sunday, February 22, 2015

#320 Atomic-scale technology - horizontally!

What is even more impressive than the atomic-scale manipulation of vertical dimensions (see previous blog) is our ability to manipulate semiconductors and other solids  and to create horizontal atomic-scale geometries.


While in the vertical manipulations atom-by-atom deposition is relatively easy to implement these days, definition of horizontal nano-geaometries depends entirely on the resolution of the lithographic processes and precision of the follow up etching processes. In spite of the all so well recognized lithography resolution's related challenges, atomic-scale definition of the horizontal features is the reality.


Just consider for instance less than 10 nm wide "fins" formed on the wafer surface during the FinFET fabrication. Based on the numbers considered in the previous blog, a 5 nm "fin" is an about 20 atoms wide. In top-down processes it is a combination of the resolution of the lithographic process and precision of subsequent etching process that makes it possible.


Posted by Jerzy Ruzyllo at 05:36 PM | Semiconductors | Link

‹‹ ›› is the personal blog of Jerzy Ruzyllo. With over 35 years of experience in academic research and teaching in the area of semiconductor engineering (currently holding position of a Distinguished Professor of Electrical Engineering and Professor of Materials Science and Engineering at Penn State University), he has a unique perspective on the developments in this progress driving technical domain and enjoys blogging about it.

With over 2000 terms defined and explained, Semiconductor Glossary is the most complete reference in the field of semiconductors on the market today.

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