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Sunday, February 11, 2018

#383 Semiconductor Glossary

In the case you would be interested in my "Semiconductor Glossary" in either hard copy or ebook version check this site.

Posted by Jerzy Ruzyllo at 07:25 PM | Semiconductors | Link


Sunday, January 28, 2018

#382 Potential barrier

Following on the concept of potential barrier mentioned in previous blog.

 

The most obvious way to create a potential barrier in semiconductors is to bring to contact two semiconductors with different work functions.  Actually, these may be two pieces of the same material such as silicon, providing however, each of them is doped at the different level and/or feature different conductivity type (p-type semiconductor and n-type semiconductor), and thus, feature different work function.  A potential barrier is formed in the piece of semiconductor in the absence of the voltage bias when p-type and n-type semiconductors are brought into contact to form a structure known as a p-n junction.

 

Posted by Jerzy Ruzyllo at 08:52 PM | Semiconductors | Link


Sunday, January 14, 2018

#381 Constructing semiconductor device

There are two fundamental features that are indispensable elements in the making of the functional semiconductor device. First, it needs to be assured that the electric current can flow in and out of semiconductor comprising a device in the entirely undisturbed fashion. To accomplish this task, ohmic contacts need to be formed at the device input and output.

 

Assuming ohmic contacts are in place, second feature making active semiconductor device is building into it an ability to vary in the controlled fashion its resistance by applying bias voltage between device terminals. To accomplish this last feature a potential barrier must be built into the device structure. The most common way of accomplishing it is to form a p-n junction within semiconductor material.

Posted by Jerzy Ruzyllo at 05:49 PM | Semiconductors | Link


Sunday, December 17, 2017

#380 What is "semiconductor device"?

The term “semiconductor device” is referring to the piece or a thin-film of semiconductor material, combined as needed with thin layers of insulators and conductors, which is configured in such way that it can perform in the controlled fashion predetermined electronic, photonic, or electro-mechanical functions. Electronic functions are performed by electronic devices which operation is based on the interactions of electric charge carriers and in which electrons are acting as information/energy carriers. Term photonic devices is concerned with devices involving interactions of photons (“packets” of electromagnetic energy carried by light) and in which photons are acting as information/energy carriers.  Finally, electro-mechanical devices are taking advantage of the mechanical characteristics, such as elasticity and fracture toughness of some semiconductor materials, silicon in particular.

 

In contrast to electronic and photonic functions,  which involve interactions solely within semiconductor material systems, electro-mechanical functions require involvement of solids capable of converting mechanical action into electrical signal such as piezoelectrics which convert mechanical stress into electrical signal and vice versa.

 

Posted by Jerzy Ruzyllo at 03:15 PM | Semiconductors | Link


Sunday, December 3, 2017

#379 The concept of "equivalent gate length" (EGL) is bound to come

The Equivalent Oxide Thickness (EOT) is a number (in nm) which expresses thickness of the SiO2 gate oxide that is needed to obtain the same capacitance of the MOS gate stack as the one obtained with physically thicker than SiO2, but featuring higher than SiO2 dielectric constant k.

 

Here, I suggest the term Equivalent Gate Length (EGL) as the represenation of the same as EOT idea, but used in relation to the MOSFETs gate scaling process.

 

It appears that scaling of the physical gate length in advanced CMOS ciruits below 5 nm  may be practical only under some special circumstances. Yet, the progress beyond 5 nm technology node will continue except that by means of vastly expanding pool of materials used to construct transistor and by drastically modifying its architecture rather than by gate scaling. When those times will come the term Equivalent Gate Length will be very handy. As an example, EGL = 1 nm would mean that the transistor performance equivalent to the performance of the ficticious transistor featuring gate length of 1 nm can be in some situations accomplished using MOSFETs with longer physical gate length such as for instance 7 nm.

 

Posted by Jerzy Ruzyllo at 02:15 PM | Semiconductors | Link


Sunday, November 26, 2017

#378 IEDM 2017

As usual at this time of the year, a quick update regarding this year IEDM (IEEE International Electron Device Meeting).

Time: Dec. 2-6, 2017

Place: San Frncisco Hilton

Porgram: click here.

 

Consider checking it out to see current trends in broadly understood semiconductor science and engineering.

Posted by Jerzy Ruzyllo at 04:49 PM | Semiconductors | Link


Sunday, November 5, 2017

#377 Moore's law is slowing down, but...

Speaking of trends in advanced semiconductor technology, a mother of all trends, namely Moor's law is no longer working like a clockwork it used to be for the last 50+ years. It is actually slowing down which means changes in advanced IC engineering are introduced at the rate slower than  predicted by Moor's law. 

 

What is really interesting, however, is that this process does not necessarily applies across all product lines. What may look like a slow down, or even Moore's law coming to the halt soon, in the world of chips for supercomputers and servers, does not necessarily apply to the world of chips for mobile communication devices.  Click here to get to the story which explains dynamics of the Moor's law slow down in more details.

Posted by Jerzy Ruzyllo at 03:20 PM | Semiconductors | Link


Sunday, October 15, 2017

#376 Some trends are no longer followed

Comments in my previous blog were concerned with semiconductor industry defying the process of Si wafers up-sizing, process which for the last 40 or so was like clockwork.

 

It looks like we are in the era in which some established trends in advanced semiconductor engineering are coming to an end. The reasons are related to either physical barriers, or to technical challenges, or to business aspects of any given venture. Do you remember how the reduction of the thickness of gate oxide in MOSFETs from initial ~100 nm in early ’70 was essentially on automatic until it came to a screeching halt at around 1 nm some ten years ago? (look for examples of  other trends of the similar nature in coming blogs)

 

Posted by Jerzy Ruzyllo at 09:03 AM | Semiconductors | Link


Sunday, October 8, 2017

#375 450 mm? No so fast...

450 mm diameter silicon wafers in production seemed not long ago like a done deal. Well, as it turns out not exactly. It looks like big semiconductor industrial players are one by one postponing/cancelling (for now?) plans to switch to 450 mm platform. What it means is that their bottom line will continue doing ok without going through the very costly transition from 300 mm to 450 mm wafers.

 

To an old-timer such as myself it is a very interesting, and in the way much telling situation. I follow smooth transitions from one Si wafer size to another since a switch from 4 inch (100 mm) to 5 inch wafer size some 40 years ago and it is for a very first time that the transition is so “bumpy”, extended over long period of time, and overall uncertain. So, long live 300 mm? 

 

Posted by Jerzy Ruzyllo at 04:26 PM | Semiconductors | Link


Sunday, September 24, 2017

#374 Could an overall academic experience of student athletes be enhanced?

Essentially all major research universities also have strong athletic programs which means research and athletic communities are supposedly sharing their academic experiences. Well, not necessarily. While research faculty and students are mostly well aware of the ups and downs of the teams and individual athletes representing university, the latter are mostly are not given an opportunity to learn about  research activities on campus.

 

There are things that can be easily done to mediate this situation. I have no doubts researchers would be ready to take time to introduce to the students athletes their research and research facilities on campus. No class schedule, no credits, no mandatory attendance, etc., just an opportunity to learn what’s going on in the buildings  they might be walking by every day without knowing what is being done inside.

Posted by Jerzy Ruzyllo at 06:06 PM | Semiconductors | Link


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Semi1source.com/blog is the personal blog of Jerzy Ruzyllo. With over 35 years of experience in academic research and teaching in the area of semiconductor engineering (currently holding position of a Distinguished Professor of Electrical Engineering and Professor of Materials Science and Engineering at Penn State University), he has a unique perspective on the developments in this progress driving technical domain and enjoys blogging about it.



With over 2000 terms defined and explained, Semiconductor Glossary is the most complete reference in the field of semiconductors on the market today.






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