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Sunday, February 7, 2021

#460 Vertical integration rules

 

Since the beginning of IC technology, the goal was to squeeze geometrical features of transistors and interconnects comprising ICs horizontally. And we were all happy because not only smaller transistors (including shorter gate length) performed better in terms of speed and electrostatics, but also Moore’s Law concerned with a number of transistors/chip was satisfied in the process.

 

Obviously, horizontal scaling could not continue forever and going vertical turned out to be an answer. First, good while ago, interconnects went multilevel keeping up with the needs of rapidly growing ICs complexity without having to reduce geometry of the line. Then, for the reasons discussed in my blog #458, transistor’s channel was turned vertically resulting in a FinFET. Now, transistor’s fin is split into nanosheet channels stacked up vertically. At the same time packaging technology is decidedly going 3D further enforcing a concept of vertical integration.

 

With all of the above number of transistors per chip will keep on increasing. What if it would double about every two years?

 

Posted by Jerzy Ruzyllo at 11:13 AM | Semiconductors | Link


Sunday, January 31, 2021

#459 Thirty years ago: January 1991

 

Based on the papers published in the January 1991 issue of IEEE Electron Device Letters it seems that the device research community at that time was increasingly interested in the effects potentially altering operation of the scaled down MOSFET such as those related to hot-carrier stress. Note that at that time term “deep-submicron” was used in reference to 38 micrometer technology and 11 nm was a thickness of gate oxide in advanced MOSFETs.

 

In the Solid-State Science and Technology section of the January 1991 issue of the Journal of the Electrochemical Society there are quite a few papers on the use of diffusion to dope silicon both single crystal and polycrystalline. And yes, there were also papers on the use of ion implantation, but not to dope silicon, but GaAs in which case doping by diffusion is not working because of temperature constraints. As far as doping of silicon is concerned, diffusion still remained as a dominant doping method at that time. As a matter of fact, in this very issue of JES there were two papers on the use of solid planar diffusion sources of phosphorous I happened to co-author. 

 

Posted by Jerzy Ruzyllo at 07:32 PM | Semiconductors | Link


Sunday, January 17, 2021

#458 It is all about gate capacitance

With so much discussion about MOSFEs architecture, high mobility materials, technology nodes, "fins", nanosheets etc., there is no mention of capacitance of the MOS gate stack being a driving force behind all this. The point is that the gate stack’s capacitance density needs to be maintained at the sufficiently high level to keep MOSFET’s electrostatics work. With not enough capacitive coupling between gate contact and near-surface silicon, channel cannot be induced. And no induced channel means no transistor. The problem is that with the reduced gate length, which was for years a lead element in the search  for the faster switching transistors, area of the MOSFET’s gate contact, and thus gate capacitance is decreasing and capacitance of the gate stack is decreasing.

 

The first response to this challenge was to switch to the gate dielectrics featuring dielectric constant higher than 3.9 of SiO2 instead of continuing with gate SiO2 thickness reduction (needed to keep gate capacitance sufficiently high for transistor to work) to the level at which harnessing leakage tunnel current was no longer possible.


This trick solved the gate capacitance problem for a time being, but at certain point it became obvious that material solutions are not enough and transistor architecture needs to be modified. That’s when the planar channel was turned on its site and the FinFET came to live. In this configuration gate was surrounding channel on two side, then three sides (tri-gate also known as a π-gate, then Ω-gate) and the resulting gate capacitance sufficient to turn transistor “on” at the low gate voltages was accomplished.

 

The more recent effort to keep gate capacitance density sufficiently high is the gate all-around (GAA) approach in which gate dielectric surrounds the channel in  FinFET configuration entirely.  Again, in order to maximize gate capacitance, and thus, to maintain control over transistor’s electrostatics.   In its latest version (with nanowire channels considered in the meantime), it is accomplished by using discrete silicon nanosheets (or nanoribbons) stacked up and each surrounded by the gate dielectric instead of gate dielectric surrounding vertically continuous “fin”. All to assure sufficiently high density of gate capacitance at the reduced area occupied by the transistors. So, adequate capacitive coupling of the MOS gate  was, and continues to be, a challenge and  HKMG technology, fins, GAA, and nanosheets  were coming in response.

 

Posted by Jerzy Ruzyllo at 10:43 AM | Semiconductors | Link


Sunday, January 10, 2021

#457 Problems with "technology node" terminology

It is not clear to me why the term “technology node”, certainly useful reference to the progress in digital IC technology, continues to be expressed in nanometers without any obvious connection to the size of the specific feature of the transitor or circuit.


Was it somewhere around 32 nm that the number in nm defining “technology node” and actual physical length of the transistor’s gate stopped being synomymous? Or was it even earlier than that? In any case, without some connection to the improved transistor's performance or architecure modifications we, casual observers can understand, but are unaware of, technology node expressed in nanometers does not seem to serve a constructive purpose.

 

May be the concept of the Equivalent Gate Length (EGL) I considered in blogs #379 (12/3/2017) and #422 (8/9/2020) would help establish connection between business terminology and physical reality and give us some sense of continuity in the progress of digital ICs technology? Term “X nm EGL Technology Node” where X would be defined by solid modelling and simulation could do the trick in my mind. 

 

 P.S. Most of what I am saying above was not occurring to me three years ago when I was writing a brief section on integrated circuits in my book published in early 2020.  Well, technology is plowing ahead and on occasion we are late seeing things the right way, particularly in the case when terminology is not helping to understand what is going on.

Posted by Jerzy Ruzyllo at 10:16 AM | Semiconductors | Link


Sunday, December 27, 2020

#456 A word about perovskites

The term “perovskites” is used in so many contexts these days that there seems to be a bit of misunderstanding with what these materials are all about. So, for those who are not familiar with what this class of solids represents, here is a quick word about perovskites.

 

Perovskites are distinguished as a separate class of materials not based on their strictly defined chemical makeup, or any physical characteristics, or specific applications. The term perovskite refers to the class of crystals which follow the crystal structure of a mineral calcium titanium oxide CaTiO3 and known as a perovskite structure.

 

And this is basically it. Other than that, perovskites may show up in nature or be synthetized in the lab in the number of combinations in terms of chemical composition. What follows is a divers range of physical properties and resulting applications. For instance, on one hand perovskites are materials with a great potential in solar cells applications while on the other, with some compositional modifications, are the materials displaying dielectric and ferroic properties. 

 

Either way, in the case of perovskites crystallographic structure is a common denominator. This is in contrast to other classes of materials where chemical composition is a deciding factor, for instance III-V compounds. 

 

Posted by Jerzy Ruzyllo at 05:15 PM | Semiconductors | Link


Sunday, December 20, 2020

#455 Thirty years ago: December 1990

First thing I took note of while reviewing December 1990 issue of the Journal of the Electrochemical Society was a paper entitled “An Overview of Dry Etching Damage and Contamination” authored by my Penn State colleague Stephen J. Fonash. Steve was a recognized expert in the field of post-RIE damage and his paper contains information which is relevant even thirty years later.

 

Moving to the different territory, fact that December 1990 issue of IEEE Transactions on Electron Devices was a Special Issue on the Optical and Electron-Beam Control of Semiconductor Switches indicate that already 30 years ago the need for integration of photonic and electronic functions, in this case using light to control electronic switches, was recognized.

 

December 1990 issue of Semiconductor International in turn raises the issue of the need for the MBE (Molecular Beam Epitaxy) tools moving from the research labs to the production facilities. As we know, it did happen big time over the years. Other than that, selective deposition of 0.1 µm wide copper lines was a big deal in the pre-damascene era.

 

With anticipated need for the SOI (Silicon-On-Insulator) substrates, December ’90 issue of Solid-State Technology was featuring SIMOX  (Separation by  IMplanted OXygen or Separation by IMplantation of OXygen depending on the source) technology as a solution to the possible mass production of SOI wafers. It was before wafer bonding in general and “smart cut”TM technique in particular started to gain momentum in SOI wafers technology.

 

Finally, I cannot help but to toot my own horn by pointing to my December 1990 contribution in the form of the paper published in the Technical Digest of 1990 IEDM entitled “Dry Cleaning Procedures for Silicon IC Fabrication” and co-authored by my Ph.D. advisee (at that time) Dave Frystak, and my Texas Instruments (sponsor of this research) colleague Allen Bowling. Honestly, thirty years ago we were convinced that gas-phase cleaning of silicon wafers was a solution to all silicon cleaning challenges. Well, as future did demonstrate, may be not all challenges, but certainly in some applications, especially in integrated processing dry cleaning method came very handy.

Posted by Jerzy Ruzyllo at 08:05 PM | Semiconductors | Link


Sunday, December 13, 2020

#454 My graphene story 2008-2020

Recently, while reviewing for unrelated reason my blogs posted over the years, I realized I may have my very own graphene story to tell. Here it is, based on the blogs selected from the range of my comments on this hot topic starting twelve years ago.

 

The very first time I commented on graphene, it was in three blogs posted in April 2008. Just like everybody else I was raving about this single-atom thick carbon’s potential in semiconductor electronics. I was even more enthusiastic in December 2009 following the 2009 IEDM paper exploring graphene’s potential in very high frequency, RF circuitry applications.

 

Then, two years later I came up with a series of blogs (Jan.-Aug. 2011) which seem to indicate that I was becoming a bit more cautious about ability of graphene to serve as a panacea for the problems nagging semiconductor electronics and photonics. For instance, I was commenting on graphene’s lack of energy gap as being a potential problem and peel-off technique freeing graphene form graphite as not being a solution compatible with mainstream semiconductor device technology. In my last graphene blog in 2011 (August), I was a bit more direct with my skepticism stating that the potential of graphene in digital electronics is questionable because in the transistor structure graphene, as a semi-metal, just won’t let itself to be turned “off” completely.

 

As it turns out, I did not comment on graphene directly until June 2015 which in retrospect makes me think that nothing outstanding has been happening in graphene R&D during this time period (just to make sure, this is coming from the perspective of a neutral observer never directly involved in graphene-related research). In the meantime, however, I did take a note of the 2D competitors of graphene. First came the comment on molybdenum disulfide, MoS2, (Dec. 2012) which, in contrast to graphene features energy gap and is showing good promise in transistor applications. Then, in February 2013, I alluded to 2D silicon known as silicene which was behind, at least at that time, in terms of development, but by the virtue of being a silicon was, and continue to be my favorite (I am a “silicon guy”, by the way, and I may not be totally objective). Also, a form of carbon in between graphene and diamond, known as diamane caught my attention in February 2014.

 

Coming back to graphene, it was in June 2015 when I took note of the fact that some key electronic properties of graphene such as impressively high electron mobility, apply to the free-standing graphene only. When in physical contact with other material(s), which has to be the case when graphene is formed or deposited on solid surfaces to form functional devices, those outstanding electronic properties seem to downgrade significantly. I know, they are ways to work around this issue, but they complicated processing of graphene-based devices in a major way.

 

In February 2019 I posted my most recent graphene related blog in which I objected to the use of the term “graphene solar cells”. Why? Because in so-called graphene solar cells, graphene is playing a supporting role of the transparent contact for instance, but is not a material in which photovoltaic effect is initiated by the sunlight.

 

Don’t get me wrong, graphene, whether as a 2D sheet or in the form of 1D nanotube known as carbon nanotube (CNT) is a marvelous material and it will be, and already is, used in numerous applications including batteries, biomedicine, ITO replacing transparent contacts, packaging, sensors, supercapacitors to name just a few. Twelve years ago, I was really enthusiastic about expected graphene’s ground breaking impact in semiconductor electronics and photonics. Well, things did not turn out this way, at least not until now, but I have a strong feeling they will, in one shape or another.

 

And this is the end of my 2008-2020 graphene story.

 

Posted by Jerzy Ruzyllo at 10:25 AM | Semiconductors | Link


Sunday, November 29, 2020

#453 Thirty years ago: November 1990

 The emphasis on the search of the new solutions in broadly understood transistor technology in early 90’s continues (see blog #443). Just as yet another example, in November ’90 issue of IEEE Electron Device Letters, 16 out of 22 papers published were devoted to transistors and transistors engineering. And not only one type of transistors. The list of transistors, referred to by acronyms, in this issue of EDL is long: HEMTs both as HFETs and MODFETs, MESFETs, MOSFETs of course, but also HBTs in various forms and shapes.

 

As far as processing is concerned, focus was on 0.25 µm technology (still technology node of the future at that time) as revealed by the papers published in November 1990 issue of the Journal of Electrochemical Society. For instance, new DUV photoresist compatible with KrF excimer lasers, low temperature thermal growth of ultra-thin SiO2 gate oxides (high-k gate dielectrics were of no interest yet), shallow doping, and quite a few papers on plasma etching underscore semiconductor processing interests 30 years ago. Earlier 1990 issues of JES were, not surprisingly, showing thesame trends (e.g. see blog $493). 

 

Posted by Jerzy Ruzyllo at 08:35 PM | Semiconductors | Link


Sunday, November 22, 2020

#452 Organic semiconductors: question comes back

With Organic Light Emitting Diodes (OLED) dominating displays’ market these days, it is somewhat surprising to see how little is known about the meaning of “O” in now broadly used acronym “OLED”. So, a very brief explanation.

 

The letter “O” refers to organic materials, i.e. materials comprised of carbon and hydrogen in seemingly endless combinations and configurations, which display semiconductor properties similar to their inorganic counterparts such as elemental silicon or germanium, and many compound materials.

 

Organic semiconductors are based on either small molecules (monomers) or polymers comprised of small molecules shaped into chains. In both cases weak van der Waals forces are responsible for the cohesion of resulting plastic-like solids. In terms of chemical composition, the most commonly used representative of small-molecule organic semiconductors is pentacene, C22H44. The common polymeric organic semiconductors are conjugated polymers, i.e. polymers composed of two linked compounds. Both single-molecule and polymer semiconductors are readily available commercially.

 

Despite inferior to inorganic semiconductors electronic and photonic properties, organic semiconductors are broadly used in the range of applications because unlike typical inorganic semiconductors they allow transparent, flexible and printable electronic and photonic devices and circuits.

 

To get more insights into inorganic and organic semiconductors you may want to check my book “Guide to Semiconductor Engineering”.

Posted by Jerzy Ruzyllo at 05:57 PM | Semiconductors | Link


Sunday, November 15, 2020

#451 No quantum without nano

The general, perception appears to be that whatever “quantum” means, it represents 21st Century revolutionary innovations shattering the laws of classical physics and moving us into entirely unchartered territories. The reality is that, as discussed in the blog #449, quantum phenomena (unraveled by Bohr, Heisenberg, Schrödinger, Einstein and others some 100 years ago, by the way), are present in semiconductor device engineering for quite some time already.

 

Quantum phenomena did not have any practical bearing until we’ve developed capability to process materials in a single nanometer (nm) range (as a reminder, size of an average atom is in the range of 0.2 – 0.3 nm)  Whether it is a 5 nm long transistor’s gate where ballistic transport can take over charge transport, 1.5 nm thick gate oxide, where quantum tunneling leakage current messes up transistors operation, or 10 nm thick epitaxial layer acting as a quantum well where 2DEG (two dimensional electron gas) control device performance, or smaller than 10 nm quantum dot where any change in the dots diameter affects its fundamental properties, there is no “quantum” without “nano”. In other words, if it not were for our aggressive scientific and engineering efforts over the last half a Century aimed at the reduction of geometry of transistors in cutting edge digital ICs to a single nanometer level (developing the tools and the methods of nanotechnology in the process), quantum physics would not be a part of functional semiconductor devices engineering and the concept of quantum transistor and then quantum computing would remain in the sphere of unattainable in practice goals. So, in short, “nano” is making “quantum” feasible.

 

Posted by Jerzy Ruzyllo at 08:25 PM | Semiconductors | Link


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Semi1source.com/blog is a personal blog of Jerzy Ruzyllo. He is Distinguished Professor Emeritus in the Department of Electrical Engineering at Penn State University. With over forty years' experience in academic research and teaching in semiconductor engineering he has a unique perspective on the developments in this technical domain and enjoys blogging about it.




This book gives a complete account of semiconductor engineering covering semiconductor properties, semiconductor materials, semiconductor devices and their uses, process technology, fabrication processes, and semiconductor materials and process characterization.



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