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Saturday, December 12, 2009
More IEDM
My experience with IEDM goes back to 1977 when as a very young aprentice of semiconductor research I had my first IEDM paper. Other papers and several IEDMs, on both ends of the continent, followed. The most recent one, completed couple of days ago in Baltimore, confirmed once again my trust in IEDM as a true institution in the world of semiconductors.
As usual, I learned few things shuffling from room to room and patiently listening to numerous presentation. One development in CMOS engineering that I did not fully appreciate is a far reaching diversification of the PMOS and NMOS processes in the CMOS fabrication sequence. For years the difference was basically only in the type of source and drain doping and threshold voltage adjustment. Now, PMOS and NMOS parts are being processed as they were two separate devices. Even if high-k dielectric (typically HfO-based) and gate contact metal (typically TiN) are the same on both sides of the trench isolation the difference between PMOS and NMOS parts abound, e.g. different stressors, different work function adjusting capping materials in the gate stack, etc. The diversification, driven by the need to very precisely tailor performance of P- and N- MOSFETs, may even get to the point where one transistor in the CMOS cell will be processed following gate-first scenario (see my earlier blog) while the other will employ a gate-last scheme.
It looks to me like we are talking here a new era in CMOS technology…… Posted by Jerzy Ruzyllo at 10:25 AM |
Semiconductors
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Thursday, December 3, 2009
2009 IEDM is coming
The recognition of the IEEE International Electron Device Meeting (IEDM) as a prime technical/scientific event of the year is pretty well established in semiconductor community worldwide. Breaking with tradition, the 2009 IEDM will be held next week in Baltimore, MD, rather than in Washington, D.C. Other than this, IEDM 2009 projects itself as yet another meeting in the series worth attending.
Looking through the program it is quite obvious that the “CMOS era” continues to be in a full swing. Various structures/configurations/materials used to build transistors comprising a CMOS cell are considered (.e.g. nanowire based channels, high mobility III-Vs .....etc. ), but as a switch, CMOS does not seem to be challenged. At least not for now.... Posted by Jerzy Ruzyllo at 08:02 PM |
Semiconductors
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Tuesday, November 24, 2009
A non-semiconductor question....
Not exactly my territory, but I have a question… In my local paper I came across an information about “….proposed greenhouse gas emissions targets before the U.N. climate change summit meeting in Copenhagen…”. Why the need to control greenhouse gases emission is always mentioned in the context of climate change? Shouldn’t we control emission of these gases because they polute the air we breath? Climate change, or not? The permanent connection between CO2 emission in particular, and global warming (questioned by quite a few people, by the way) is blurring the picture with regard to this otherwise obvious need to control emission of gases which, unlike CO2, do not belong in the Earth's atmosphere. Posted by Jerzy Ruzyllo at 06:48 PM |
Semiconductors
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Wednesday, November 18, 2009
Gate first, gate last
My previous blog with regard to the selectivity of cleaning of wafers which include HK+MG gate stacks (high-k gate dielectric and metal gate contact) reminded me about an issue which does not appear to be recognized as a major shift in CMOS processing paradigm which, in reality, it is. At least from the old-timer’s vantage point…
In short, no longer a classic “gate first” sequence, i.e. the process in which MOS gate stack is formed before source and drain are defined, is the only solution. With SiO2 as a gate dielectric and poly-Si gate contact, source and drain implantation and post-implantation anneal did not cause any problems in terms of gate stack degradation. With much less robust HK+MG gate stacks and strained channels the concern is that source and drain engineering steps could cause irreversible damage. The solution pursued by some advanced logic ICs manufacturers is a “gate last” approach. In this case source, drain and stressors are processed first and only then MOS gate stack is fit where it belongs. How interesting… Posted by Jerzy Ruzyllo at 08:31 PM |
Semiconductors
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Thursday, November 12, 2009
Cleaning challenge - selectivity
“Selectivity” was always an issue in etch technology where etching of one material should not affect other materials on the surface of the wafer. “Selectivity” was not a top-of-the-list issue during standard cleaning operations of silicon wafers. That is not until MOS gates structures in state-of-the-art CMOS technology (45 nm and below) have become complex, multi-material mazes involving various high-k dielectrics with capping layers and metal gate contacts.
Regardless of whether such gate stacks involve dual-metal, single-dielectric (DMSD) or single-metal, dual-dielectric (SMDD) configurations the post-resist stripping clean up, that must follow gate stack delineation, has become a real challenge. Coming up with cleaning chemistry which will be benign with respect to such a divers range of materials is a real problem. Good times when during cleaning operations, even in the most advanced processes, we were dealing with just a silicon (substrate wafer and poly-Si gate contact) and silicon dioxide are gone. Posted by Jerzy Ruzyllo at 08:59 PM |
Semiconductors
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Monday, November 2, 2009
Challenges in advanced wafer cleaning
Papers presented during recent ECS Semiconductor Cleaning symposium in Vienna (see previous entry), as well as other current semiconductor cleaning related publications identify numerous challenges this important part of semiconductor manufacturing process is facing.
For instance, as vertical dimensions of the device continue to shrink, the material losses and surface roughening during cleaning operations have become a real problem in surface preparation technology. The process of particle removal without material loss and pattern damage must involve serious tradeoffs. Physical aids such as megasonic agitation, potentially a key problem in terms of structural damage, is being re-engineered so that efficiency of the particle removal process will be maintained without pattern damage
Considering the fact that an atomic scale deterioration of surface morphology may have a "killer" effect on device performance, even seemingly the most benign elements of the cleaning sequence, such as DI water rinse, must be re-evaluated from this point of view. Posted by Jerzy Ruzyllo at 07:38 PM |
Semiconductors
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Saturday, October 24, 2009
Semiconductor cleaning in Vienna
The 11th International Symposium on Cleaning and Surface Conditioning Technology in Semiconductor Device Manufacturing was held during the ECS Fall Meeting in Vienna (see complete list of papers presented). I will comment on the trends emerging in this important component of semiconductor manufacturing in the forthcoming blog(s). Posted by Jerzy Ruzyllo at 06:27 PM |
Semiconductors
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Sunday, October 18, 2009
Semiconductors in Vienna
The latest ECS meeting in Vienna was good for semiconductors. It is not always the case considering “wet” component of the Electrochemical Society being stronger in terms of the membership than its “dry” (read solid-state) counterpart. In Vienna, however, the selection of strong, well established and well attended semiconductor related symposia was serving semiconductor attendees very well.
Other then “classics” such as Semiconductor Cleaning Symposium, Compound Semiconductor Symposium, or High-k Materials and Gate Stacks Symposium, new trends in semiconductor science and engineering were represented by symposia covering Semiconductors and Plasmonics, Organic Semiconductor Materials and Devices and One-Dimensional Nanoscale Electronics and Photonics. Posted by Jerzy Ruzyllo at 08:26 AM |
Semiconductors
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Wednesday, October 14, 2009
ECS meeting in Vienna
The 2009 Fall meeting of the Electrochemical Society (ECS) was held in Vienna. It was the third time the ECS ventured with its meeting to Europe. Two other times the ECS meetings were held in Paris. With just one more past ECS meeting held outside of the US (Cancun, Mexico), the ECS has quite a way to go before locations of its meetings will adequately reflect international makeup of its membership. It seems to be just a matter of time before ECS will locate one of its gatherings in Asia or in South America. Posted by Jerzy Ruzyllo at 08:44 PM |
Semiconductors
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Wednesday, September 30, 2009
Nanodots go mainstream
I don't recall any semiconductor material finding practical applications just as a piece of material. In other words, I don't recall semiconductor being used in the form other than a highly processed device performing specific electronic or photonic functions.
With nanocrystalline quantum dots (see entry of Sept. 23) this paradigm is changing. The prime example would be an increasingly common use of ZnO nanoparticles in sunscreens. With its wide bandgap (see my comments on ZnO posted on July 29, 2008) ZnO acts as an effective absorber of UVA (400 nm - 320nm) which is the main component of UV radiation in the sunlight. Featuring negligible physical dimensions the nanodots do not alter in any way smoothness of the sunscreen base.
There chance is we will see more and more uses of semiconductor nanodots in applications which have nothing to do with electronic or photonic devices. And this is certainly good for semiconductors....
Posted by Jerzy Ruzyllo at 08:24 PM |
Semiconductors
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