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Sunday, September 28, 2014

#306 Is there a role for tin?

In spite of sitting in the same group 14 of the periodic table of element as the elemental semiconductors carbon, silicon and germanium and featuring the same diamond crystal structure, tin (chemical symbol Sn because of its Latin name stannum) does not display semiconductor properties that would allow it on its own to be of use in the mainstream semiconductor device applications. With energy gap of just 0.1 eV and melting point of 232oC, tin does not offer much in this respect.


Well, it is not the end of the tin story, though. First, simulation and early experiments indicate that by forming a germanium-tin alloy, GeSn, with 3% of Sn added to Ge, a semiconductor which converts indirect bandgap of Ge into direct bandgap and increases hole mobility of Ge is formed. It certainly sounds interesting from both electronic and photonic potential applications point of view.


Second, a single layer of tin atoms called stanene (from stannum and graphene) should feature, according to theoretical physicists, outstanding electrical conductivity around room temperature potentially making it a great interconnect material in future generation ICs. While it all is still in an early stage of development the chances are that tin, a neglected in high end semiconductor applications group 14 element, will be attracting more attention as the time goes by.

Posted by Jerzy Ruzyllo at 07:48 AM | Semiconductors | Link

Sunday, September 21, 2014

#305 One-year M.S. degree program.

Responding to the need to streamline M.S. (Master of Science) level programs at major U.S. research universities my department (Electrical Engineering) at Penn State just introduced a One-Year M.S. degree program track for Fall 2015. 


Go to the program description in the case you, or someone you know, would be interested. Applications to the program will be accepted from October 1, 2014 through December 15, 2014.


Posted by Jerzy Ruzyllo at 08:03 PM | Semiconductors | Link

Sunday, September 14, 2014

#304 Revolution? Evolution?

I recently needed to go back to the fundamentals of solid state physics upon which modern semiconductor science and engineering are built. As a result, once again I did realize how long was the process which brought us to where we are with the knowledge base in this key to our lives technical domain.


We like to call the process that followed invention of transistor by Bardeen, Brattain and Shockley over 60 years ago an electronics revolution implying that it all started with successful demonstration of transistor action. That’s fine, but question I have is how did Bardeen, Brattain and Shockley know to apply two gold contacts in specific configuration to the crystal of germanium in their search of the elusive “transistor action”? Obviously they were not moving in the dark, but were making their choices drawing from the prior knowledge, knowledge that did take half a century to evolve and mature to the point where a working transistor could be demonstrated.


To give credit to where credit is due we need to go back to the very beginnings of 20th century when Planck came up with his quantum hypothesis, validity of which was then unequivocally confirmed by Einstein. Then came de Broglie with his wave-particle duality principle, Schrodinger who brought it all together with a wave mechanics formulation and Pauli who announced his exclusion principle. Quarter century after Planck’s seminal contribution, Fermi-Dirac’s statistics, with the name of the first one used to identify key to this statistics concept of a Fermi level, got the solid state physics to the point when scientifically sound considerations regarding solid-sate replacement of the vacuum triode, a replacement later called a “transistor”, were possible. It is not the coincidence that about that time Lilienfeld patented a three-electrode structure using copper-sulfide semiconductor material, and known today as a field-effect transistor.


In spite of all this it took scientists and engineers another quarter century to actually bring working transistor, in the different form than the one envisioned by Lilienfeld, to life. Now, you pass your own judgment, was it a “revolution” or “evolution”? Not that it really matters, but it is fun to look back and to reflect on  what does it actually take to produce technical breakthroughs.

Posted by Jerzy Ruzyllo at 11:59 AM | Semiconductors | Link

Sunday, September 7, 2014

#303 Wafer thickness

Just to make it clear, my comment in the previous blog regarding increasing thickness of the substrate wafers needed to assure adequate mechanical stability of still larger wafers, applies to advanced IC manufacturing using high-quality single-crystal silicon wafers.


Considering exuberant cost of an advance IC design, masks, manufacturing processes etc., the cost of somewhat more silicon being used to make the wafer thicker is almost marginal. At the same time, thickness of the wafer has basically no effect of the operation of an integrated circuit formed within very shallow region at the wafers top surface.


Considerations regarding thickness of the substrate wafers in photovoltaics, in other words substrate wafers used to manufacture solar cells, are drastically different  (well, yes, they are square rather than circular ones used in IC manufacturing, but it’s not a point).


First, in the case of solar cells the cost of material is the major portion of manufacturing costs. Any reduction of the cost of material resulting from using thinner substrates, i.e. less material, translates directly into the decrease of the cost of energy generated by solar cells. From this point of view, substrate wafer, Si for instance, should be as thin as possible. Second, thickness of the substrate wafer matters also because it affects the efficiency of conversion of solar energy into electricity by impacting light absorption characteristics of the material. Except that in this case thinner is better only up to certain point and making wafer too thin will actually hurt cell’s performance


Considering all of the above (and making a long story short), an optimum thickness of Si substrate wafers used in photovoltaics should be somewhere around 50 µm. As the thinnest wafers used now to manufacture solar panels are about 150 µm thick, photovoltaics industry is faced with significant challenges on its way to the sub-100 µm wafer thickness regime. It’s not easy to manufacture such ultra-thin wafers and it’s even more difficult to handle them during subsequent solar cells manufacturing processes due to their extreme fragility.




Posted by Jerzy Ruzyllo at 05:11 PM | Semiconductors | Link

Sunday, August 31, 2014

#302 Wafers not only are getting larger

Comment about Si wafers in IC manufacturing getting larger in previous blog made me think about the aspect of the increasing wafer size which often goes unnoticed.


From the process engineering perspective an important consequence of the wafers getting larger in diameter is a significantly increasing weight of the wafer. For instance, 450 mm wafer is about 4x heavier than its 200 mm predecessor (~ 200 g and ~53 g respectively). Corresponding weights of the 13-wafers batches are 689 g and ~2,600 g which from the wafer handling infrastructure perspective makes tremendous difference. Not to mention increased thickness of the larger wafers necessary to assure their mechanical stability. This element also requires major upgrading of the wafer handling robots, cassettes, etc.


Posted by Jerzy Ruzyllo at 05:50 PM | Semiconductors | Link

Sunday, August 17, 2014

#301 Scaling up

As it applies to transistor’s geometry in logic applications the term “scaling” unanimously implies scaling down, i.e. making it smaller and smaller according to the technology driving theme “shorter the gate the better”. Well, the issue of “scaling” is not all that simple in semiconductor science and engineering these days.


First, in most of the transistors other than those for logic and memory applications geometry scaling down is not an issue. Just think power transistors or Thin-Film Transistors (TFT) in all their variations which are all perfectly comfortable in the µm technology regime. 


Second, there is actually a lot of scaling up going on in semiconductor engineering these days. Wafers in IC manufacturing are getting larger, reaching 45 cm in 2015, PV panels bigger, and displays as well (all of which, by the way, puts a scale-up demands on the process tools). Think also lighting panels getting bigger and bigger, roll-to-roll processes, wearable electronics and photonics, etc. etc.


In conclusion, you don’t need to be a devotee of “scaling down” paradigm to represent cutting edge in semiconductor science and engineering. Miniaturization is not exactly a buzz word in the world of semiconductors these days…

Posted by Jerzy Ruzyllo at 04:20 PM | Semiconductors | Link

Sunday, August 10, 2014

#300 How to work around transistor scaling?

A theme that seems to dominate these days semiconductor electronics chatter  in variouspublications, conference presentations and informal discussions is focused on the futureof transistor scaling, or more accurately, on how to work around the need for scaling andstill keep on improving performance of logic ICs. In other words, scaling is no longer seen as a main technology driver. To many of you it doesn’t look like a big deal, but to the old-timers such as myself, who grew up with the notion that progress is synonymous with transistor scaling,  all this looks almost like a revolution.


Whether through innovative transistor architectures (see e.g blog #288) or new materials solutions, or most likely combination of these two elements, I have no doubts whatsoever that the solution(s) to this apparent deadlock will be found. It is just a matter of time (and needs, which means money).


A side note: It is my blog #300. A nice, even number with no consequences other than reminding me that I am in the "business" of semiconductor blogging for over 7 years now.


Posted by Jerzy Ruzyllo at 11:11 PM | Semiconductors | Link

Sunday, August 3, 2014

#299 Misuse of the term "semiconductors"

In business and financial communities the term "Semiconductors" is quite commonly used in reference to the industry concerned with development and manufacturing of advanced integrated circuit.


How misleading and inaccurate it is... I would have no problem with "semiconductor electronics", but to use the name of the entire class of materials in reference to only one type of products these materials are used to manufacture? How about optoelectronic devices including lasers and LEDs for lighting applications, photovoltaics, not to mention MEMS for instance?


Well, I don't get it. And I don't think this blog will change anything in this regard, but at least I expressed my opinion.

Posted by Jerzy Ruzyllo at 05:33 PM | Semiconductors | Link

Sunday, July 27, 2014

#298 Mist deposition

In blog #296 I mentioned other than spin-on physical liquid deposition methods including mist deposition. The idea behind mist deposition is to convert liquid precursor (for instance colloidal solution containing nanodots or viscous liquid such as  photoresist) into a very fine mist which is then carried by nitrogen to the deposition chamber where submicron droplets uniformly coalesce at room temperature and at atmospheric pressure on the wafer surface. The film is then subjected to thermal curing, just like a spin-coated material, and solidified.


Mist deposition has been proven useful in various thin-film formation applications including nanocrystalline quantum dot films, high-k dielectric films or photoresist.  


The method is particularly in the thickness regime below 100 nm where other PLD methods such as spin-on or microspray may not allow sufficient control over film thickness.

Posted by Jerzy Ruzyllo at 08:13 PM | Semiconductors | Link

Sunday, July 20, 2014

#297 An example of application

I was asked a question about thin film formation using colloidal solutions, flexible substrates and how it all may come together. Here is an example concerned with nanocrystalline quantum dot based LEDs on flexible substrate.


Posted by Jerzy Ruzyllo at 10:38 AM | Semiconductors | Link

‹‹ ›› is the personal blog of Jerzy Ruzyllo. With over 35 years of experience in academic research and teaching in the area of semiconductor engineering (currently holding position of a Distinguished Professor of Electrical Engineering and Professor of Materials Science and Engineering at Penn State University), he has a unique perspective on the developments in this progress driving technical domain and enjoys blogging about it.

With over 2000 terms defined and explained, Semiconductor Glossary is the most complete reference in the field of semiconductors on the market today.

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