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Sunday, May 9, 2021

#469 Confusing terminology

If you find news about “10-7-5-2 nm technologies” confusing, you are not alone. As a neutral observer with interest in #semiconductorengineering, I don’t see how current “nm nod” terminology is serving any useful purpose other than creating opportunities for marketing blitzes.


Nanometer is a unit of length. So, it makes sense only in reference to specific geometrical features of the transistor or interconnect scheme, and not necessarily in the context of "nm node" business endeavors, right? Well, you would think so.


In the world of advanced digital IC it seams to be free for all. The number of nm, whatever it represents, needs to be smaller. It’s all that matters. “5” is better than “7”, right? Well, how do we know? What does 10 nm nod of company X mean? How does it compare to 7 nm nod of company Y? Is 10 nm necessarily not as good as 7 nm in terms of manufacturability, reliability, performance in real circuits applications, and cost? Who knows? Some of those chips are not on the market yet.


For quite some time I was naively thinking, again as a neutral observer, that the technology node refers to transistors gate length. Only not long ago I realized that technology nodes and gate length parted ways somewhere around 32 nm- 45 nm. But how can one rationally compare technologies, if depending on the company, nanometer measures different things? Half-pitch? Pitch? Separation between transistors? Some numbers are referring to geometries of interconnects scheme, some to transistor itself? For instance, is there any feature sized at 2 nm in the recently announced by IBM 2 nm technology breakthrough?


Why don’t we adopt for good a number of transistors per unit area of the chip (not per chip) as a measure of technological complexity of the chip, and hence, technology advancement? It was suggested by knowledgeable people on several occasions in the past and is often provided. And the number defining circuit density will grow with the progress in technology as opposed to “technology nods” defined as 10, 7, 5, 2, … then 1(?), then… what?



 This entry is a continuation of the blog posted on January 10, 2021.

Posted by Jerzy Ruzyllo at 03:48 PM | Semiconductors | Link is a personal blog of Jerzy Ruzyllo. He is Distinguished Professor Emeritus in the Department of Electrical Engineering at Penn State University. With over forty years' experience in academic research and teaching in semiconductor engineering he has a unique perspective on the developments in this technical domain and enjoys blogging about it.

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