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Sunday, February 7, 2021

#460 Vertical integration rules


Since the beginning of IC technology, the goal was to squeeze geometrical features of transistors and interconnects comprising ICs horizontally. And we were all happy because not only smaller transistors (including shorter gate length) performed better in terms of speed and electrostatics, but also Moore’s Law concerned with a number of transistors/chip was satisfied in the process.


Obviously, horizontal scaling could not continue forever and going vertical turned out to be an answer. First, good while ago, interconnects went multilevel keeping up with the needs of rapidly growing ICs complexity without having to reduce geometry of the line. Then, for the reasons discussed in my blog #458, transistor’s channel was turned vertically resulting in a FinFET. Now, transistor’s fin is split into nanosheet channels stacked up vertically. At the same time packaging technology is decidedly going 3D further enforcing a concept of vertical integration.


With all of the above number of transistors per chip will keep on increasing. What if it would double about every two years?


Posted by Jerzy Ruzyllo at 11:13 AM | Semiconductors | Link is a personal blog of Jerzy Ruzyllo. He is Distinguished Professor Emeritus in the Department of Electrical Engineering at Penn State University. With over forty years' experience in academic research and teaching in semiconductor engineering he has a unique perspective on the developments in this technical domain and enjoys blogging about it.

This book gives a complete account of semiconductor engineering covering semiconductor properties, semiconductor materials, semiconductor devices and their uses, process technology, fabrication processes, and semiconductor materials and process characterization.

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