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Sunday, January 17, 2021

#458 It is all about gate capacitance


With so much discussion about MOSFEs architecture, technology nodes, fins, sheets vs. wires, etc., etc., there is little attention given to capacitance of the MOS gate stack. And the gate stack’s capacitance density needs to be maintained at the sufficiently high level to keep MOSFET’s electrostatics work. With not enough capacitive coupling between gate contact and near-surface silicon, channel cannot be induced. And no induced channel, no transistor. The problem is that with the reduced gate length, which is a driving force behind the search for the faster switching transistors, area of the MOSFET’s gate contact, and thus, gate capacitance is decreasing and capacitance of the gate stack is decreasing.


Our first response to this challenge was to switch to the gate dielectrics featuring dielectric constant higher than 3.9 of SiO2 instead of continuing with gate SiO2 thickness reduction (needed to keep gate capacitance sufficiently high for transistor to work) to the level at which harnessing tunnel leakage current was no longer possible.

This trick solved the gate capacitance problem for a time being, but at certain point it became obvious that material solutions are not enough and transistor architecture needs to be modified. That’s when the planar channel was turned on its site and the FinFET came to live. In this configuration gate is surrounding channel on three sides (tri-gate also known as a π-gate, then Ω-gate) and the resulting gate capacitance sufficient to turn transistor “on” at the low gate voltages is accomplished.


The most recent effort to keep gate capacitance density sufficiently high is the gate all-around (GAA) approach in which gate dielectric surrounds the channel entirely.  In its latest version (with nanowire channels considered in the meantime) it is accomplished by using a discreet silicon nanosheets (or nanoribbons) stacked up and each surrounded by the gate dielectric instead of gate dielectric surrounding vertically continuous “fin”. All to assure sufficiently high density of gate capacitance at the reduced area occupied by the transistors. So, capacitive coupling of the MOS gate is the real name of the game. HKMGs, fins, GAAs, sheets, etc. come in response.


Posted by Jerzy Ruzyllo at 10:43 AM | Semiconductors | Link is a personal blog of Jerzy Ruzyllo. He is Distinguished Professor Emeritus in the Department of Electrical Engineering at Penn State University. With over forty years' experience in academic research and teaching in semiconductor engineering he has a unique perspective on the developments in this technical domain and enjoys blogging about it.

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