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Sunday, August 9, 2020

#422 Equivalent Gate Length (EGL)

Scaling of the gate length of the MOSFETs comprising advanced logic ICs was for the last fifty years a main tool used to improve transistor’s performance in terms of speed of operation, on/off ratio, circuit density and others. Obviously, shortening of the gate length cannot continue indefinitely and at certain point needed improvements in transistors’ performance will have to accomplished employing other “tools”.


In the blog #379 posted in December 2017, I proposed a concept of the Equivalent Gate Length (EGL) meant to establish connection between gate scaling as a way to improve transistor performance, and alternative solutions involving modifications of transistor architecture and/or material choices potentially resulting in the comparable to gate scaling performance improvements, but implemented without reducing gate length.


Recently announced by Intel expected 20% improvement in transistor performance accomplished by re-engineering of the FinFET while maintaining the gate length at 10 nm is an example of the latter.


I wonder how much the gate length would have to be reduced to accomplish the same 20% improvement in transistor performance. In other words, what would be EGL in the case of the proposed innovative 10 nm “SuperFin” transistor architecture? 7 nm, which would mean full-node improvement, or may be 8 nm? It would be interesting to know this number to better understand the extent of this improvement.

Posted by Jerzy Ruzyllo at 10:40 AM | Semiconductors | Link is a personal blog of Jerzy Ruzyllo. He is Distinguished Professor Emeritus in the Department of Electrical Engineering at Penn State University. With over forty years' experience in academic research and teaching in semiconductor engineering he has a unique perspective on the developments in this technical domain and enjoys blogging about it.

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