After some twenty years of unobstructed progress through MOSFET’s (CMOS) channel/gate length scaling, in early 1990’s anticipated future challenges of digital IC technology were getting attention. The trend was exemplified by some papers published in May 1990 issue of IEEE Transactions on Electron Devices discussing undesired physical phenomena associated with channel length scaling in submicrometer CMOS devices, jointly referred to as “short-channel effects”. Specifically, Drain-Induced Barrier Lowering (DIBL), and hot-carrier degradation in the lower submicrometer devices were considered.

On the other hand, May 1990 issue of the Journal of the Electrochemical Society addressed a broad range of materials and processes related problems including metallization (tungsten silicide, nickel coatings, Au contacts to SiC), dielectrics (borosilicate intermetal dielectric, silicon nitride on GaAs and on InP), range of topics concerned with III-V compound device technology, for instance GaN films prepared by MOVPE, as well as with etching processes (for instance RIE induced deep levels, chemically assisted ion beam etching, or anisotropic photoetching of III-V compounds).