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Sunday, August 17, 2014

#301 Scaling up

As it applies to transistor’s geometry in logic applications the term “scaling” unanimously implies scaling down, i.e. making it smaller and smaller according to the technology driving theme “shorter the gate the better”. Well, the issue of “scaling” is not all that simple in semiconductor science and engineering these days.


First, in most of the transistors other than those for logic and memory applications geometry scaling down is not an issue. Just think power transistors or Thin-Film Transistors (TFT) in all their variations which are all perfectly comfortable in the µm technology regime. 


Second, there is actually a lot of scaling up going on in semiconductor engineering these days. Wafers in IC manufacturing are getting larger, reaching 45 cm in 2015, PV panels bigger, and displays as well (all of which, by the way, puts a scale-up demands on the process tools). Think also lighting panels getting bigger and bigger, roll-to-roll processes, wearable electronics and photonics, etc. etc.


In conclusion, you don’t need to be a devotee of “scaling down” paradigm to represent cutting edge in semiconductor science and engineering. Miniaturization is not exactly a buzz word in the world of semiconductors these days…

Posted by Jerzy Ruzyllo at 04:20 PM | Semiconductors | Link is the personal blog of Jerzy Ruzyllo. With over 35 years of experience in academic research and teaching in the area of semiconductor engineering (currently holding position of a Distinguished Professor of Electrical Engineering and Professor of Materials Science and Engineering at Penn State University), he has a unique perspective on the developments in this progress driving technical domain and enjoys blogging about it.

With over 2000 terms defined and explained, Semiconductor Glossary is the most complete reference in the field of semiconductors on the market today.

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