back to S1S home

Sunday, March 16, 2014

#280 Lattice strain

Among less than fully versed "semiconductorers" there seems to be a bit of a confusion regarding the purpose of introducing strain in the crystallographic structure in the channel of the MOSFET (being part of the CMOS cell in high end logic ICs). Well, it's all physics. In the strained lattice, effective mass of an electron is smaller than in a relaxed lattice (again, check your physics). Smaller effective mass means higher mobility of electron which means electrons in the strained channel can move from the source to the drain of the transistor faster, i.e. you get faster operating transistor.


In other words, to shorten transition time between points A and B (gate length) you can shorten the distance (which requires major improvements in the resolution of pattern definition technology which is synonymous with major changes in photolithography technology) or make carriers move faster. Strain in the crystal lattice of the channel of the transistor accomplishes the latter.

Posted by Jerzy Ruzyllo at 08:25 PM | Semiconductors | Link is the personal blog of Jerzy Ruzyllo. With over 35 years of experience in academic research and teaching in the area of semiconductor engineering (currently holding position of a Distinguished Professor of Electrical Engineering and Professor of Materials Science and Engineering at Penn State University), he has a unique perspective on the developments in this progress driving technical domain and enjoys blogging about it.

With over 2000 terms defined and explained, Semiconductor Glossary is the most complete reference in the field of semiconductors on the market today.

‹‹ May 2018 ››
W Mo Tu We Th Fr Sa Su
18 1 2 3 4 5 6
19 7 8 9 10 11 12 13
20 14 15 16 17 18 19 20
21 21 22 23 24 25 26 27
22 28 29 30 31      

Copyright © 2018 J. Ruzyllo. All rights reserved.