At various times over the years, various elements of semiconductor science and engineering were defining progress. Not long ago, when silicon was a sole ruler, the progress was riding mainly on the shoulders of improvements in process technology. At that time, developments that were punctuating the advancements were basically synonymous with what was going on in high-end logic and memory IC technology.
In the very old days ion implantation pushing aside doping by diffusion was a hit (even earlier diffusion replaced alloyed junctions by the way), then RIE came about as a savior in etch technology, then its HDP version, then CMP, supercritical fluid cleaning, etc. And of course photolithography with its developments was continuously looming over the horizon –steppers, g-line, i-line, excimer lasers, phase shift masks, immersion lithography were defining the progress.
While all this was happening not much was changing in materials (with an exception of copper replacing aluminum as an interconnect material) and device configuration. It was all based on silicon (single-crystal Si, poly-Si, SiO2, Si3N4) and planar CMOS was a device benchmark.
During the last decade or so the paradigm has shifted significantly. It is all about the materials and elaborately configured materials systems these days. Even the latest process technology related breakthrough, introduction of ALD into the mainstream manufacturing, was driven solely by the material related needs (introduction of high-k gate dielectrics). Other than that, on both ends of the line, front and back, high-end material and device engineering determine the progress. For instance, high mobility channel materials, SiGe and SiC stressors, high-k dielectric gate stack engineering, new generation of ILDs , TSVs, etc,etc.…. Even silicon substrate itself must be heavily engineered to meet emerging needs. Furthermore, needs of photovoltaics, organic semiconductor technology, printed large area electronics and photonics, flexible substrates, MEMS/NEMS, opportunities in advancements in TFT technology, 2D (graphene for instance), 1D (nanowires), zeroD (nanodots) material systems, ferromagnetic semiconductors etc. etc., spread semiconductor innovation efforts well beyond mainstream digital IC territory.
All this is breathing fresh air into semiconductor research. It is no longer that one must have 300 mm wafer capability, at least class 10 clean-room and 193 nm exposure tools to do research that have any relevance. The window for innovations is wide open and the reliance on the highest end tool is lesser than in not too remote past. Let’s hope funding will be sufficient to allow semiconductor R&D community to fully spread its wings
