My experience with IEDM goes back to 1977 when as a very young aprentice of semiconductor research I had my first IEDM paper. Other papers and several IEDMs, on both ends of the continent, followed. The most recent one, completed couple of days ago in Baltimore, confirmed once again my trust in IEDM as a true institution in the world of semiconductors.
As usual, I learned few things shuffling from room to room and patiently listening to numerous presentation. One development in CMOS engineering that I did not fully appreciate is a far reaching diversification of the PMOS and NMOS processes in the CMOS fabrication sequence. For years the difference was basically only in the type of source and drain doping and threshold voltage adjustment. Now, PMOS and NMOS parts are being processed as they were two separate devices. Even if high-k dielectric (typically HfO-based) and gate contact metal (typically TiN) are the same on both sides of the trench isolation the difference between PMOS and NMOS parts abound, e.g. different stressors, different work function adjusting capping materials in the gate stack, etc. The diversification, driven by the need to very precisely tailor performance of P- and N- MOSFETs, may even get to the point where one transistor in the CMOS cell will be processed following gate-first scenario (see my earlier blog) while the other will employ a gate-last scheme.
It looks to me like we are talking here a new era in CMOS technology……
