My previous blog with regard to the selectivity of cleaning of wafers which include HK+MG gate stacks (high-k gate dielectric and metal gate contact) reminded me about an issue which does not appear to be recognized as a major shift in CMOS processing paradigm which, in reality, it is. At least from the old-timer’s vantage point…
In short, no longer a classic “gate first” sequence, i.e. the process in which MOS gate stack is formed before source and drain are defined, is the only solution. With SiO2 as a gate dielectric and poly-Si gate contact, source and drain implantation and post-implantation anneal did not cause any problems in terms of gate stack degradation. With much less robust HK+MG gate stacks and strained channels the concern is that source and drain engineering steps could cause irreversible damage. The solution pursued by some advanced logic ICs manufacturers is a “gate last” approach. In this case source, drain and stressors are processed first and only then MOS gate stack is fit where it belongs. How interesting…
