“Selectivity” was always an issue in etch technology where etching of one material should not affect other materials on the surface of the wafer. “Selectivity” was not a top-of-the-list issue during standard cleaning operations of silicon wafers. That is not until MOS gates structures in state-of-the-art CMOS technology (45 nm and below) have become complex, multi-material mazes involving various high-k dielectrics with capping layers and metal gate contacts.
Regardless of whether such gate stacks involve dual-metal, single-dielectric (DMSD) or single-metal, dual-dielectric (SMDD) configurations the post-resist stripping clean up, that must follow gate stack delineation, has become a real challenge. Coming up with cleaning chemistry which will be benign with respect to such a divers range of materials is a real problem. Good times when during cleaning operations, even in the most advanced processes, we were dealing with just a silicon (substrate wafer and poly-Si gate contact) and silicon dioxide are gone.
