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Sunday, December 3, 2017

#379 The concept of "equivalent gate length" (EGL) is bound to come

The Equivalent Oxide Thickness (EOT) is a number (in nm) which expresses thickness of the SiO2 gate oxide that is needed to obtain the same capacitance of the MOS gate stack as the one obtained with physically thicker than SiO2, but featuring higher than SiO2 dielectric constant k.

 

Here, I suggest the term Equivalent Gate Length (EGL) as the represenation of the same as EOT idea, but used in relation to the MOSFETs gate scaling process.

 

It appears that scaling of the physical gate length in advanced CMOS ciruits below 5 nm  may be practical only under some special circumstances. Yet, the progress beyond 5 nm technology node will continue except that by means of vastly expanding pool of materials used to construct transistor and by drastically modifying its architecture rather than by gate scaling. When those times will come the term Equivalent Gate Length will be very handy. As an example, EGL = 1 nm would mean that the transistor performance equivalent to the performance of the ficticious transistor featuring gate length of 1 nm can be in some situations accomplished using MOSFETs with longer physical gate length such as for instance 7 nm.

 

Posted by Jerzy Ruzyllo at 02:15 PM | Semiconductors | Link


Sunday, November 26, 2017

#378 IEDM 2017

As usual at this time of the year, a quick update regarding this year IEDM (IEEE International Electron Device Meeting).

Time: Dec. 2-6, 2017

Place: San Frncisco Hilton

Porgram: click here.

 

Consider checking it out to see current trends in broadly understood semiconductor science and engineering.

Posted by Jerzy Ruzyllo at 04:49 PM | Semiconductors | Link


Sunday, November 5, 2017

#377 Moore's law is slowing down, but...

Speaking of trends in advanced semiconductor technology, a mother of all trends, namely Moor's law is no longer working like a clockwork it used to be for the last 50+ years. It is actually slowing down which means changes in advanced IC engineering are introduced at the rate slower than  predicted by Moor's law. 

 

What is really interesting, however, is that this process does not necessarily applies across all product lines. What may look like a slow down, or even Moore's law coming to the halt soon, in the world of chips for supercomputers and servers, does not necessarily apply to the world of chips for mobile communication devices.  Click here to get to the story which explains dynamics of the Moor's law slow down in more details.

Posted by Jerzy Ruzyllo at 03:20 PM | Semiconductors | Link


Sunday, October 15, 2017

#376 Some trends are no longer followed

Comments in my previous blog were concerned with semiconductor industry defying the process of Si wafers up-sizing, process which for the last 40 or so was like clockwork.

 

It looks like we are in the era in which some established trends in advanced semiconductor engineering are coming to an end. The reasons are related to either physical barriers, or to technical challenges, or to business aspects of any given venture. Do you remember how the reduction of the thickness of gate oxide in MOSFETs from initial ~100 nm in early ’70 was essentially on automatic until it came to a screeching halt at around 1 nm some ten years ago? (look for examples of  other trends of the similar nature in coming blogs)

 

Posted by Jerzy Ruzyllo at 09:03 AM | Semiconductors | Link


Sunday, October 8, 2017

#375 450 mm? No so fast...

450 mm diameter silicon wafers in production seemed not long ago like a done deal. Well, as it turns out not exactly. It looks like big semiconductor industrial players are one by one postponing/cancelling (for now?) plans to switch to 450 mm platform. What it means is that their bottom line will continue doing ok without going through the very costly transition from 300 mm to 450 mm wafers.

 

To an old-timer such as myself it is a very interesting, and in the way much telling situation. I follow smooth transitions from one Si wafer size to another since a switch from 4 inch (100 mm) to 5 inch wafer size some 40 years ago and it is for a very first time that the transition is so “bumpy”, extended over long period of time, and overall uncertain. So, long live 300 mm? 

 

Posted by Jerzy Ruzyllo at 04:26 PM | Semiconductors | Link


Sunday, September 24, 2017

#374 Could an overall academic experience of student athletes be enhanced?

Essentially all major research universities also have strong athletic programs which means research and athletic communities are supposedly sharing their academic experiences. Well, not necessarily. While research faculty and students are mostly well aware of the ups and downs of the teams and individual athletes representing university, the latter are mostly are not given an opportunity to learn about  research activities on campus.

 

There are things that can be easily done to mediate this situation. I have no doubts researchers would be ready to take time to introduce to the students athletes their research and research facilities on campus. No class schedule, no credits, no mandatory attendance, etc., just an opportunity to learn what’s going on in the buildings  they might be walking by every day without knowing what is being done inside.

Posted by Jerzy Ruzyllo at 06:06 PM | Semiconductors | Link


Sunday, September 17, 2017

#373 Silicon carbide is now

While carbon may still be semiconductor of the future (see previous blog),  a compound of carbon with silicon (silicon carbide, SiC) is making big splashes in the mainstream semiconductor device technology.

 

 SiC, also known as carborundumm, is a semiconductor material which features wide energy gap and high thermal conductivity, high breakdown field. and high saturated electron drift velocity. This combination of characteristics offer superior performance of SiC devices in high temperature/high power applications, as well as in high speed operation under high electric field conditions.  All together this features make SiC device technology  a significant commercial success.

Posted by Jerzy Ruzyllo at 03:47 PM | Semiconductors | Link


Sunday, July 9, 2017

#372 Carbon is still semiconductor of the future

Speaking of elemental semiconductors (see previous blog), in contrast to silicon, carbon  in the form of diamond is having problems getting into the mainstream semiconductor technology. This is in spite of its in many ways superior to silicon physical characteristics such as width of the energy gap, thermal conductivity, and others,. But, unfortunately, one shortcoming related to the n-type doping challenges (click here for an expert assessment of diamond electronics). 

 

Things may change for the better because unlike no other solid element, carbon can be obtained and explored in all geometrical configuration including  3D diamond, 2D graphene, 1D carbon nanotubes, and 0D carbon quantum dots. Between these four configurations carbon displays a number of very attractive characteristics. So, if not diamond, them may be nanototubes or graphene. Or may  be quantum dots….

 

For now however, carbon still is a semiconductor of the future.

 

Posted by Jerzy Ruzyllo at 04:23 PM | Semiconductors | Link


Sunday, June 18, 2017

#371 Silicon is forever

Few thoughts regarding role of silicon in electronics and photonics. Once considered a semiconductor material to be gradually replaced by other semiconductors, silicon defies all odds and its role continues to expand into new areas.  

 

Obviously, silicon is a truly abundant element displaying decent semiconductor characteristics (plus excellent mechanical properties which make it uniquely suitable for MEMS/NEMS applications). However, it is not silicon’s abundance or physical characteristics that is a main driving force behind its most recent expansion, but the fact that it can be processed into very large chemically pure wafers (up to 450 mm in diameter) which are mechanically very sturdy and essentially defects-free. This set of characteristics makes silicon a highly desired substrate for semiconductors which themselves cannot be obtained in the form of such large wafers among which gallium nitride, GaN, which is a foundation of LED-based lighting technology, is a prime example.  

Posted by Jerzy Ruzyllo at 10:57 AM | Semiconductors | Link


Sunday, May 21, 2017

#370 Surface matters

As indicated in the previous blog, impact of the surface on the properties of semiconductor sample is not limited to the single-atom plane at the surface, but extends to the near-surface region. In practice such near-surface region  can be significantly disturbed structurally by surface roughness and process related physical damage as well as it can be significantly altered in terms of its chemical makeup all of which causes its impact to penetrate deep into the crystal.

 

Considering all this, it is clear that electronic properties in the near-surface region of any solid, including semiconductors, depart significantly from the same properties in the bulk. For instance, due to the increased scattering of charge carriers resulting from the defective lattice and electrically charged centers in the near-surface region, mobility of carriers moving close to the surface is reduced significantly as compared to the bulk.

 

Posted by Jerzy Ruzyllo at 08:08 AM | Semiconductors | Link


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Semi1source.com/blog is the personal blog of Jerzy Ruzyllo. With over 35 years of experience in academic research and teaching in the area of semiconductor engineering (currently holding position of a Distinguished Professor of Electrical Engineering and Professor of Materials Science and Engineering at Penn State University), he has a unique perspective on the developments in this progress driving technical domain and enjoys blogging about it.



With over 2000 terms defined and explained, Semiconductor Glossary is the most complete reference in the field of semiconductors on the market today.






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