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Sunday, September 5, 2021

#478 Lateral MIS Tunnel Transistor

 As discussed in the previous blog, MIS tunnel diode provides alternative to p-n junction and Schottky diode way of controlling current flowing across potential barrier built into bulk of semiconductor material or formed on its surface. And just like p-n junctions are at the core of Bipolar Junction Transistor (BJT) technology, and Schottky diodes are used to construct Metal-Semiconductor Field Effect Transistors (MESFET), MIS tunnel diodes can be also employed to form devices performing transistor functions. Unlike conventional MOSFET, however, MIS tunnel transistor is using both majority and minority carriers to operate, and thus falls into category of bipolar transistors.

 

MIS tunnel transistors were first considered by Schewchun and Clarke in early 1970’s as Surface Oxide Transistors (SOT).  Few years later, author of this blog in the paper published in IEEE Electron Device Letters suggested, under the name Lateral MIS Tunnel Transistor (LMISTT) alternative, lateral structure,  featuring all three contacts (two MIS tunnel diodes and the ohmic contact) on the top surface of silicon wafer, and was able to experimentally demonstrate its working. At that time, in the era of total focus of MOSFET/CMOS technology and no limits seen with regard to how far this technology can take us, this contribution went essentially unnoticed.

 

Here, I revive the concept of this particular transistor configuration because it may come handy in implementing transistors on new generation thin-film and nanoscale semiconductor materials both inorganic and organic, flexible or not, which some forty years ago were not even considered for any device applications.  Specifically, materials which (i) are not compatible with elevated temperature processing as to deposit LMISTT’s 2-3 nm thick layer of insulator low-temperature ALD can be used and no doping is required, (ii) are not compatible with standard photolithographic processes as micrometer scale LMISTT can be fabricated using mechanical masks with no wet steps involved, and (iii) do not form Schottky contacts with readily available metals which makes them incompatible with MESFET technology.

 

Feel free to contact me on LinkedIn if you would be interested in additional information regarding LMISTT.

 

Posted by Jerzy Ruzyllo at 08:29 PM | Semiconductors | Link


Sunday, August 29, 2021

#477 MIS tunnel junction diode

As discussed in my Guide to Semiconductor Engineering (see also here), operation of two-terminal semiconductor device is based on the ability to control the current flowing across it by either varying concentration of free charge carriers available for conduction (resistors), or by creating a potential barrier height of which depends on the applied voltage and affects the flow of charge carriers (diodes). 

 

The potential barrier needed to make an active two-terminal semiconductor device is commonly obtained either by the formation of the p-n junction (p-n junction diode), or by bringing to contact properly selected metal and semiconductor (metal-semiconductor, or M-S junction also known as Schottky diode).  

 

The third option involves structures in which metal and semiconductor are separated by ultrathin (in a thickness range of 3 nm) layer of insulator, typically an oxide. Because of its limited thickness, and under proper bias conditions, current can flow between metal and semiconductor by electrons tunneling across the oxide. Just like in the case of p-n junction and Schottky contacts, density of such current depends on the direction of the applied voltage. Devices of this type are referred to as MIS (Metal-Insulator-Semiconductor) tunnel junction diodes, or MIS tunnel diodes in short.  

 

MIS tunnel diodes are rarely used in the implementation of practical devices mainly because p-n junction and Schottky diodes are successfully fulfilling their roles. However, there are situations in which whether because of the limited thermal stability of semiconductor material, its geometry, or lack of metals forming Schottky contacts on its surface, MIS tunnel diode configuration as a potential barrier contriling structure may come useful. This usefulness extends into transistor technology and leads to the MIS Tunnel Transistor to be briefly introduced next time.

Posted by Jerzy Ruzyllo at 05:08 PM | Semiconductors | Link


Sunday, August 15, 2021

#476 Thirty years ago: August 1991

 

Precise measurements of temperature of wafers subject to thermal treatments in the course of semiconductor device manufacturing was always a challenge. Whether high-temperature oxidation or epitaxial deposition, or low-temperature anneal, whether IR heating or inductive heating, control of wafer temperature was a challenge. The challenge was particularly drastic in the case of Rapid Thermal Processing (RTP) making inroads into mainstream semiconductor manufacturing technology some thirty years ago.

 

In August 1991 issue of the trade magazine “Semiconductor International” challenges of wafer temperature measurement in the course of the rapid heating of processed wafers are considered and commercial RTP systems available on the market at that time compared.Type of pyrometers employed, material used to construct the reactor and its shape, as well as the way emissivity correction was implemented were the factors distinguishing between various commercial RTP tools.

 

Posted by Jerzy Ruzyllo at 10:23 AM | Semiconductors | Link


Sunday, August 8, 2021

#475 Electrical characterization of perovskite

 

In December last year (blog #464) I posted quick comments regarding growing impact of semiconductor materials featuring perovskite structure, and known as perovskites. In March this year in turn (blog #464), I was elaborating on the potential of crystals electrical characterization employing RF-based, non-contact electrical measurement system.

 

There is no doubt in my mind the latter could be very effective in sorting out very fine structural defects-related issues in perovskite semiconductors applied for instance in photovoltaics.

 

There is one problem, though. Somebody will need to invest and build a tool to carry out these measurements.  See here what can be done in this regard.

 

Posted by Jerzy Ruzyllo at 02:09 PM | Semiconductors | Link


Sunday, July 25, 2021

#474 Thirty years ago: July 1991

Not much new comparing to the main themes of the research papers published earlier in 1991.


Focus was still on HBTs (Heterojunction Bipolar Transistors), built on multilayer III-V semiconductors structures. Occasional ventures into silicon germanium (SiGe) territory, which was a novelty in practical applications at that time, are noted. Not surprisingly, with deposition of thin-film, single-crystal compounds at the core of HBT technology, experiments with Molecular Beam Epitaxy (MBE) and Metalorganic Chemical Vapor Deposition (MOCVD) were at the center of attention of semiconductor processing research community back then.

 

As far as MOSFET is concerned, in anticipation of the challenges of gate oxide scaling, experiments aimed at the mastering of ultra-thin SiO2 continued world-wide.

Posted by Jerzy Ruzyllo at 05:46 PM | Semiconductors | Link


Sunday, July 11, 2021

#473 Nitrides

This is to take note of nitrides as increasingly go to semiconductors in applications requiring wide bandgap.

 

The III-V compounds are typically classified based on the group V element forming a compound into nitrides, phosphides, arsenides and antimonides. In this class of compound semiconductors gallium nitride, GaN, is of key importance in both electronic and photonic devices. Outstanding characteristics of GaN is its direct and wide (Eg = 3.5 eV) energy gap. These bandgap’s characteristics make GaN uniquely suitable for the emission of short wavelength light in the blue range. As a result, and in addition to the lack of other single-crystal semiconductors featuring similar characteristics, GaN is a cornerstone material in blue and white light emitting semiconductor devices. Furthermore, wide bandgap makes it highly suitable for high-power/high-temperature device applications. The GaN technology is still somewhat hampered by the lack of free standing, low-cost, large area single-crystals GaN substrates upon which devices can be built In the light of these limitations, GaN devices are fabricated using thin-film GaN deposited on the substrates made out of the other materials including sapphire, silicon carbide, and silicon.  

 

Among other III-V nitrides, boron nitride, BN, and aluminum nitride, AlN, are attracting attention due the largest, direct energy gap among all semiconductor compounds (BN Eg = 6.4 eV, AlN Eg = 6.2 eV,). However, at the low electron mobility (BN µ =200 cm2/vs, AlN µ =300 cm2/Vs) their use in commercial devices is limited primarily to UV detection. Indium nitride, InN, on the other hand features rather narrow bandgap  (Eg ~ 0.7eV) and relatively high electron mobility µ = 3,200 cm2/vs. Still, InN is best used when alloyed with GaN to form InGaN.

Posted by Jerzy Ruzyllo at 01:14 PM | Semiconductors | Link


Sunday, June 20, 2021

#472 Thirty years ago: June 1991

 

At the device side, based on the contents of June 91’ issue of the IEEE Electron Device Letters, it was very much about speedy alternatives to conventional MOSFETs. At that time CMOS was already established low-power switching solution in the mainstream digital IC technology, but its speed of operation limitations were prompting efforts geared toward other, potentially faster transistor configurations. Representing these “search for speed” efforts were reports on HBTs (Heterojunction Bipolar Transistor), HEMTs (High Electron Mobility Transistor), and MESFETs (Metal Semiconductor FET), all constructed based on III-V compounds.  

 

At the process/materials end of semiconductor engineering spectrum, papers published in June 91’ issue of the Journal of Electrochemical Society did not show any clearly identifiable trends. Everything was on the table, thermal oxidation and rapid thermal annealing, diffusion and epitaxial growth. May be two papers dealing with elaborate ellipsometric methods allowing measurements of thickness of ultrathin (<10 nm) oxides could be seen as being focused on a single well defined challenge. Gate oxide in MOSFETs was getting thinner and thinner and improved methods of spectroscopic ellipsometry allowing precise measurements of oxide thickness were needed.

 

Posted by Jerzy Ruzyllo at 09:18 PM | Semiconductors | Link


Sunday, June 6, 2021

#471 Wafer bonding

 Wafer bonding is a process which permanently bonds (fuses) two wafers into a single mechanically coherent substrate without using adhesives.  This versatile technique allows formation of semiconductor substrates which are difficult to obtain using other methods. 

 

fer bonding technology can solve variety of problems. For instance, not all semiconductors can be obtained as single-crystals in the size and shape compatible with wafering. With wafer bonding, pieces of such material can be bonded to larger wafer which will provide mechanical support and facilitate its during device fabrication processes.

 

In the process of wafer bonding two wafers featuring the same chemical com position and crystallographic structure, for instance two silicon wafers, or two single-crystal wafers of different materials featuring mismatched crystal lattices, for instance GaN and Si, can be bonded into a single substrate. Furthermore, in wafer bonding technology two wafers involved do not have to be semiconductors. Bonding wafers of silicon and sapphire, which when bonded form a silicon-on-sapphire (SOS) substrate, is an example.

 

 

 For more on susbtrates used in semiconductor manufacturib check here.

Posted by Jerzy Ruzyllo at 12:07 PM | Semiconductors | Link


Sunday, May 30, 2021

#470 More on the role of MOS gate capacitance

A precondition for the properly working MOSFETs (Metal-Oxide-Semiconductor Field Effect Transistors), which rule digital IC technology regardless of technology node, is adequate capacitive coupling between gate contact and silicon. In other words, density of MOS gate capacitance needs to be sufficiently high to keep transistor work while it is being reduced in size to pack more transistors per unit area of the chip.

 

Seeing evolution of the MOSFET during the last 15 years through the prism of the density of MOS gate stack capacitance, the following three stages can be identified:  (i) replacing thinned to the limit SiO2 as a gate oxide with higher dielectric constant material to allow increased physical thickness of the gate dielectric, (ii) modifying transistor architecture and using “fin” configuration to increase gate area at the reduced transistor foot print, and (iii) employing nanoscaled silicon in the form of stacked-up nanosheets to address challenges facing next generations of MOSFET-based digital electronics.

 

Some more on the role of MOS gate capacitance in the blog posted on January 17, 2021

 

Posted by Jerzy Ruzyllo at 10:00 AM | Semiconductors | Link


Sunday, May 9, 2021

#469 Confusing terminology

If you find news about “10-7-5-2 nm technologies” confusing, you are not alone. As a neutral observer with interest in #semiconductorengineering, I don’t see how current “nm nod” terminology is serving any useful purpose other than creating opportunities for marketing blitzes.

 

Nanometer is a unit of length. So, it makes sense only in reference to specific geometrical features of the transistor or interconnect scheme, and not necessarily in the context of "nm node" business endeavors, right? Well, you would think so.

 

In the world of advanced digital IC it seams to be free for all. The number of nm, whatever it represents, needs to be smaller. It’s all that matters. “5” is better than “7”, right? Well, how do we know? What does 10 nm nod of company X mean? How does it compare to 7 nm nod of company Y? Is 10 nm necessarily not as good as 7 nm in terms of manufacturability, reliability, performance in real circuits applications, and cost? Who knows? Some of those chips are not on the market yet.

 

For quite some time I was naively thinking, again as a neutral observer, that the technology node refers to transistors gate length. Only not long ago I realized that technology nodes and gate length parted ways somewhere around 32 nm- 45 nm. But how can one rationally compare technologies, if depending on the company, nanometer measures different things? Half-pitch? Pitch? Separation between transistors? Some numbers are referring to geometries of interconnects scheme, some to transistor itself? For instance, is there any feature sized at 2 nm in the recently announced by IBM 2 nm technology breakthrough?

 

Why don’t we adopt for good a number of transistors per unit area of the chip (not per chip) as a measure of technological complexity of the chip, and hence, technology advancement? It was suggested by knowledgeable people on several occasions in the past and is often provided. And the number defining circuit density will grow with the progress in technology as opposed to “technology nods” defined as 10, 7, 5, 2, … then 1(?), then… what?

 

 

 This entry is a continuation of the blog posted on January 10, 2021.

Posted by Jerzy Ruzyllo at 03:48 PM | Semiconductors | Link


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Semi1source.com/blog is a personal blog of Jerzy Ruzyllo. He is Distinguished Professor Emeritus in the Department of Electrical Engineering at Penn State University. With over forty years' experience in academic research and teaching in semiconductor engineering he has a unique perspective on the developments in this technical domain and enjoys blogging about it.




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