back to S1S home

Sunday, April 4, 2021

#467 III-VI compounds

Members of semiconductor community, whether associated with teaching, research, or manufacturing, are familiar with man-made semiconductor compounds formed using elements from groups II to VII of the periodic table. The IV-IV compound semiconductors (SiC, SiGe), III-V compound semiconductors (e.g. GaAs, InAs, GaN, etc.), as well as II-VI compound semiconductors (e.g. ZnO, CdTe, CdSe etc.) are all well-known and most of them are broadly used in practical applications.


Another class of compounds based on the same elements of the periodic table but in III-VI combination is not getting the same attention as those listed above. One feature differentiating III-VI compounds from others formed using elements from groups II to VII of the periodic table is that III-VIs feature between two contributing elements forming the compound a total of nine valence electrons (III+VI). This is in contrast to all other compounds originating from these groups with eight valence electrons between elements forming a compound (IV+IV, III+V and II+VI). As a result, it takes more complex (in terms of interatomic bonding scheme), material systems to accommodate differences in electronic structure between contributing elements resulting in compounds such as Ga2O3, Al2O3, In2Te3 and others.


What is also not helping III-VI compounds to be seen as a self-contained class of materials is that unlike most of those other compounds featuring semiconductor properties, some III-VI compounds display  advantageous semiconductor properties (e.g. Ga2O3) while some others are flat out excellent insulators (e.g. Al2O3).


More on this topic next time…


Posted by Jerzy Ruzyllo at 05:26 PM | Semiconductors | Link

Sunday, March 28, 2021

#466 Semiconductor material selection criteria

Often encountered question is why certain semiconductor material is suitable for any given device application while other is not. List of the device implications of select physical characteristics of semiconductor materials is fairly long (see Guide to Semiconductor Engineering (, so here are just three key characteristics. 


Energy gap width -  in electronic devices wide bandgap (e.g. SiC) allows better handling of power and temperature. In photonic devices bandgap defines light absorption and emission characteristics. A wide bandgap semiconductor (e.g. GaN) is needed to emit high energy (shorter wavelength) radiation such as blue light.


Type of energy gap – indirect bandgap semiconductor (e.g. Si) features inefficient radiative recombination which means that, without employing special “tricks”,  it is not a material suitable for the manufacture of light emitting devices. Direct bandgap semiconductors on the other hand are the materials we use to make light emitting devices such as LEDs and lasers.


Electron mobility – determines speed of electronic device operation in both digital and analog applications.

Posted by Jerzy Ruzyllo at 12:07 PM | Semiconductors | Link

Sunday, March 21, 2021

#465 Thirty years ago: March 1991

The cover story of the March ’91 issue of Solid-State Technology magazine was devoted to the large diameter silicon wafers. At that time “large” meant 200 mm wafers which were scheduled to be used in commercially significant numbers in the 1991-92 time frame. Well, 300 mm and 450 mm wafers happened between then and now, but 200 mm continue to be a go to substrate in various commercial applications.


What caught my attention while reviewing contents of the March ’91 issues of the Journal of the Electrochemical Society and IEEE Electron Device Letters was a significant number of papers concerned with GaAs (and its derivatives) processes and devices. And yes, I recall times some 30 years ago or so, when GaAs was seen as a semiconductor material of the future, sooner or later replacing silicon in all key electronic applications. Well, as we all know it didn’t happen.  

Posted by Jerzy Ruzyllo at 11:23 AM | Semiconductors | Link

Sunday, March 14, 2021

#464 Non-contact, in-line, real-time RF wafer monitoring

Electrical measurements of semiconductor materials and devices have always been, and will continue to be a key characterization methodology in semiconductor device engineering. When properly applied, electrical characterization can unequivocally determine quality of material and predict performance of device to be built using this material (trust me, I know it, I used electrical characterization in my research for some  45 years)


A challenge in this specific application is to perform electrical characterization without contacting a product wafer, or other crystalline semiconductor material, and without any interference with its characterized surface. In other word, the challenge is to perform measurements in the totally noninvasive fashion compatible with the needs of in-line, real time monitoring of processes used to manufacture semiconductor devices.


New opportunities in the area are provided by non-contact, in-line, real-time method based on the use RF radiation. If interested, and may be interested in being involved in this project,  take a look at the Defect Specific Lifetime Analysis (DSLA) method described here: GEKA ASSOCIATES (


Posted by Jerzy Ruzyllo at 08:40 PM | Semiconductors | Link

Sunday, March 7, 2021

#463 Non-semiconductor substrates

There are several semiconductor device applications in which substrates in the form of rigid, electrically conductive semiconductor wafers are not needed, or not desired. In such cases, insulating substrates are employed to provide mechanical support for semiconductor devices built on their surfaces using broadly understood thin-film technology.


In the case electronic and/or photonic devices require an insulating substrate featuring outstanding optical, mechanical, and chemical characteristics, sapphire is the first choice. Sapphire is a single-crystal (hexagonal) form of aluminum oxide Al2O3, which features substrate properties that are highly conducive with the needs of several key electronic and photonic semiconductor devices.


In the case when single-crystal material is not needed as an insulating substrate, glass is a solution. As a result, glass is the most common substrate in thin-film semiconductor device technology. It offers insulating properties, transparency to light, and adequate mechanical stability.


Both sapphire and glass substrates are mechanically rigid and as such are used only in semiconductor devices and circuits which are not subject to bending, flexing or stretching. When flexibility of the substrate is needed, bendable and rollable plastic films are the first choice


Look for more information on non-semiconductor insulating substrates used semiconductor device engineering in the Guide to Semiconductor Engineering (


Posted by Jerzy Ruzyllo at 08:32 PM | Semiconductors | Link

Sunday, February 28, 2021

#462 Thirty years ago: February 1991

Two papers in February ’91 issue of IEEE Electron Letters that attracted my attention were concerned with very different topics. First was a paper by my Penn State colleagues describing successful realization of transistor action in the thin-film diamond Field-Effect Transistor. The other one demonstrated significantly increased hole mobility in strain-controlled Si-Ge Modulation-Doped FET. It was an early indication of the possibilities to improve device performance by employing strain in the crystal lattice induced by SiGe.


At the material/process end of semiconductor research spectrum Journal of the Electrochemical Society in its February ’91 issue reported on the Reactive Ion Etching of Indium-Tin Oxide (ITO) which since then became number one transparent conductor broadly used as a contact material in various photonic devices. Also, published in this issue paper concerned with the effect of oxygen concentration on lifetime in magnetic Czochralski (CZ) grown single-crystal silicon was a confirmation of advantageous role magnetic field is playing in the CZ processes.

Posted by Jerzy Ruzyllo at 07:49 PM | Semiconductors | Link

Sunday, February 14, 2021

#461 Engineered wafers

 In the high-end silicon device manufacturing homogenous Si wafers, commonly referred to as bulk wafers, need to be engineered further to meet specific device related requirements. Directions in which wafer engineering may proceed depends on type of device wafers will be used for and include the following solutions.


Denuded zone formation Term “denuded zone” refers to the very thin part of the wafer immediately adjacent to its top surface from which some excessive structural defects and/or alien elements (contaminants) are displaced into the bulk portion of the wafer by means of the gettering processes.


Epitaxial extension Process of epitaxial deposition allows formation of the very-thin layer of single-crystal material in such way that the crystallographic structure of the deposited film exactly reproduces crystallographic structure of the substrate, yet the film is chemically purer and if grown sufficiently thick may feature the surface that is less defective than the surface of the substrate (e.g. formation of thick SiC epilayers on SiC).


Strained-layer heteroepitaxy is yet another technique that is being used to engineer substrate wafer toward building into it desired characteristics which in this case is a strained top surface layer.


Wafer bonding is a process which permanently bonds (fuses) two wafers into a single mechanically coherent substrate without using adhesives.  This versatile technique allows formation of semiconductor substrates which are impossible to obtain using other methods.  


For more information regarding wafer engineering see Guide to Semiconductor Engineering (

Posted by Jerzy Ruzyllo at 05:43 PM | Semiconductors | Link

Sunday, February 7, 2021

#460 Vertical integration rules


Since the beginning of IC technology, the goal was to squeeze geometrical features of transistors and interconnects comprising ICs horizontally. And we were all happy because not only smaller transistors (including shorter gate length) performed better in terms of speed and electrostatics, but also Moore’s Law concerned with a number of transistors/chip was satisfied in the process.


Obviously, horizontal scaling could not continue forever and going vertical turned out to be an answer. First, good while ago, interconnects went multilevel keeping up with the needs of rapidly growing ICs complexity without having to reduce geometry of the line. Then, for the reasons discussed in my blog #458, transistor’s channel was turned vertically resulting in a FinFET. Now, transistor’s fin is split into nanosheet channels stacked up vertically. At the same time packaging technology is decidedly going 3D further enforcing a concept of vertical integration.


With all of the above number of transistors per chip will keep on increasing. What if it would double about every two years?


Posted by Jerzy Ruzyllo at 11:13 AM | Semiconductors | Link

Sunday, January 31, 2021

#459 Thirty years ago: January 1991


Based on the papers published in the January 1991 issue of IEEE Electron Device Letters it seems that the device research community at that time was increasingly interested in the effects potentially altering operation of the scaled down MOSFET such as those related to hot-carrier stress. Note that at that time term “deep-submicron” was used in reference to 38 micrometer technology and 11 nm was a thickness of gate oxide in advanced MOSFETs.


In the Solid-State Science and Technology section of the January 1991 issue of the Journal of the Electrochemical Society there are quite a few papers on the use of diffusion to dope silicon both single crystal and polycrystalline. And yes, there were also papers on the use of ion implantation, but not to dope silicon, but GaAs in which case doping by diffusion is not working because of temperature constraints. As far as doping of silicon is concerned, diffusion still remained as a dominant doping method at that time. As a matter of fact, in this very issue of JES there were two papers on the use of solid planar diffusion sources of phosphorous I happened to co-author. 


Posted by Jerzy Ruzyllo at 07:32 PM | Semiconductors | Link

Sunday, January 17, 2021

#458 It is all about gate capacitance


With so much discussion about MOSFEs architecture, technology nodes, fins, sheets vs. wires, etc., etc., there is little attention given to capacitance of the MOS gate stack. And the gate stack’s capacitance density needs to be maintained at the sufficiently high level to keep MOSFET’s electrostatics work. With not enough capacitive coupling between gate contact and near-surface silicon, channel cannot be induced. And no induced channel, no transistor. The problem is that with the reduced gate length, which is a driving force behind the search for the faster switching transistors, area of the MOSFET’s gate contact, and thus, gate capacitance is decreasing and capacitance of the gate stack is decreasing.


Our first response to this challenge was to switch to the gate dielectrics featuring dielectric constant higher than 3.9 of SiO2 instead of continuing with gate SiO2 thickness reduction (needed to keep gate capacitance sufficiently high for transistor to work) to the level at which harnessing tunnel leakage current was no longer possible.

This trick solved the gate capacitance problem for a time being, but at certain point it became obvious that material solutions are not enough and transistor architecture needs to be modified. That’s when the planar channel was turned on its site and the FinFET came to live. In this configuration gate is surrounding channel on three sides (tri-gate also known as a π-gate, then Ω-gate) and the resulting gate capacitance sufficient to turn transistor “on” at the low gate voltages is accomplished.


The most recent effort to keep gate capacitance density sufficiently high is the gate all-around (GAA) approach in which gate dielectric surrounds the channel entirely.  In its latest version (with nanowire channels considered in the meantime) it is accomplished by using a discreet silicon nanosheets (or nanoribbons) stacked up and each surrounded by the gate dielectric instead of gate dielectric surrounding vertically continuous “fin”. All to assure sufficiently high density of gate capacitance at the reduced area occupied by the transistors. So, capacitive coupling of the MOS gate is the real name of the game. HKMGs, fins, GAAs, sheets, etc. come in response.


Posted by Jerzy Ruzyllo at 10:43 AM | Semiconductors | Link

›› is a personal blog of Jerzy Ruzyllo. He is Distinguished Professor Emeritus in the Department of Electrical Engineering at Penn State University. With over forty years' experience in academic research and teaching in semiconductor engineering he has a unique perspective on the developments in this technical domain and enjoys blogging about it.

This book gives a complete account of semiconductor engineering covering semiconductor properties, semiconductor materials, semiconductor devices and their uses, process technology, fabrication processes, and semiconductor materials and process characterization.

With over 2000 terms defined and explained, Semiconductor Glossary is the most complete reference in the field of semiconductors on the market today.


  GEKA Associates

Metrology Experts

Copyright © 2021 J. Ruzyllo. All rights reserved.