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Sunday, February 14, 2010
On sabbatical
It’s been a while since I posted the last blog. While on sabbatical and on the go since the beginning of the Spring semester I don’t get much time to do fun things such as occasional blogging.
For my sabbatical I ended up as a Visiting Professor at the Warsaw University of Technology in Poland. This prestigious school (Warsaw Tech in my mind), which happens to be my Alma Matter by the way, is considered to be the best technical school in Poland. I enjoy very much the experience of temporarily going back to my roots after 25 years at Penn State.
Besides working on the joint research projects, frequent seminars and workshops I’ve also got inadvertently involved in the discussion concerning reforms of the system of higher education in Poland. A major makeover has been in the plans for quite some time, but now the process has entered a stage of very extensive discussions and negotiations.
I don’t have enough of the contact with the workings of the system of higher education in Poland these days to formulate firm opinions. Still, after going through the entire process of scientific maturation in Poland (M.Sc., Ph.D, and “habilitation”) and then partially repeating it in the major research university in the US (tenure track, tenure, Associate Professorship and then Full Professorship) I can see things in somewhat special way.
One interesting difference which was always there, but which earlier didn’t catch my eye as clearly as it does now, is the process of hiring of the young assistants professors, straight after getting a Ph.D., by the Polish universities. It’s almost uniquely their own graduates that are being hired which means that for all practical purposes a Ph.D. adviser becomes a boss of the young academic apprentice. This tradition is not serving well a community as it promotes self-breeding and hampers innovative thinking and scientific independence of the youngsters. At Penn State, and it seems to be a rule in academic institutions across the US, hiring of our own Ph.Ds for academic positions is prohibited and the rule is strictly enforced.
Another observation, and again, the one that concerns something I grew up with and this something never seemed unusual to me, is a bit of a ”professormania” I did take note of not only in Poland, but in some other European countries as well. A position, or a title of a Professor itself rather than scientific/teaching excellence often appears to be a dominant goal of an academic career. Some rebalancing of priorities in this regard would serve Polish academic community well, I think.
Posted by Jerzy Ruzyllo at 04:44 PM |
Semiconductors
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Tuesday, January 12, 2010
Era of materials and eleborate material systems
At various times over the years, various elements of semiconductor science and engineering were defining progress. Not long ago, when silicon was a sole ruler, the progress was riding mainly on the shoulders of improvements in process technology. At that time, developments that were punctuating the advancements were basically synonymous with what was going on in high-end logic and memory IC technology.
In the very old days ion implantation pushing aside doping by diffusion was a hit (even earlier diffusion replaced alloyed junctions by the way), then RIE came about as a savior in etch technology, then its HDP version, then CMP, supercritical fluid cleaning, etc. And of course photolithography with its developments was continuously looming over the horizon –steppers, g-line, i-line, excimer lasers, phase shift masks, immersion lithography were defining the progress.
While all this was happening not much was changing in materials (with an exception of copper replacing aluminum as an interconnect material) and device configuration. It was all based on silicon (single-crystal Si, poly-Si, SiO2, Si3N4) and planar CMOS was a device benchmark.
During the last decade or so the paradigm has shifted significantly. It is all about the materials and elaborately configured materials systems these days. Even the latest process technology related breakthrough, introduction of ALD into the mainstream manufacturing, was driven solely by the material related needs (introduction of high-k gate dielectrics). Other than that, on both ends of the line, front and back, high-end material and device engineering determine the progress. For instance, high mobility channel materials, SiGe and SiC stressors, high-k dielectric gate stack engineering, new generation of ILDs , TSVs, etc,etc.…. Even silicon substrate itself must be heavily engineered to meet emerging needs. Furthermore, needs of photovoltaics, organic semiconductor technology, printed large area electronics and photonics, flexible substrates, MEMS/NEMS, opportunities in advancements in TFT technology, 2D (graphene for instance), 1D (nanowires), zeroD (nanodots) material systems, ferromagnetic semiconductors etc. etc., spread semiconductor innovation efforts well beyond mainstream digital IC territory.
All this is breathing fresh air into semiconductor research. It is no longer that one must have 300 mm wafer capability, at least class 10 clean-room and 193 nm exposure tools to do research that have any relevance. The window for innovations is wide open and the reliance on the highest end tool is lesser than in not too remote past. Let’s hope funding will be sufficient to allow semiconductor R&D community to fully spread its wings
Posted by Jerzy Ruzyllo at 08:42 PM |
Semiconductors
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Saturday, December 26, 2009
Graphene comes to life
Well over a year ago, on April 2, 5, and 15, 2008 to be exact, I posted few comments on graphene. I marveled about unique properties of this 2D carbon and, just like most everybody, considered it to be a very promising material for the future. Somehow, I felt good about grapahene’s prospects because I could see the path for its integration into the mainstream MOSFET technology.
During the recent IEDM, papers devoted to graphene convinced me that we are no longer talking about graphene just in terms of the “promise”. Based on the review papers presented it looks like reports on the fully functional FETs with graphene channels fabricated using various techniques, and on various substrates, abound. For instance, devices with reported cut-off frequency up to 50 GHz rather convincingly demonstrate the potential of graphene for RF applications.
Overall, I was surprised to see how advanced is the exploration of graphene in the real-life applications.
Posted by Jerzy Ruzyllo at 08:11 PM |
Semiconductors
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Saturday, December 12, 2009
More IEDM
My experience with IEDM goes back to 1977 when as a very young aprentice of semiconductor research I had my first IEDM paper. Other papers and several IEDMs, on both ends of the continent, followed. The most recent one, completed couple of days ago in Baltimore, confirmed once again my trust in IEDM as a true institution in the world of semiconductors.
As usual, I learned few things shuffling from room to room and patiently listening to numerous presentation. One development in CMOS engineering that I did not fully appreciate is a far reaching diversification of the PMOS and NMOS processes in the CMOS fabrication sequence. For years the difference was basically only in the type of source and drain doping and threshold voltage adjustment. Now, PMOS and NMOS parts are being processed as they were two separate devices. Even if high-k dielectric (typically HfO-based) and gate contact metal (typically TiN) are the same on both sides of the trench isolation the difference between PMOS and NMOS parts abound, e.g. different stressors, different work function adjusting capping materials in the gate stack, etc. The diversification, driven by the need to very precisely tailor performance of P- and N- MOSFETs, may even get to the point where one transistor in the CMOS cell will be processed following gate-first scenario (see my earlier blog) while the other will employ a gate-last scheme.
It looks to me like we are talking here a new era in CMOS technology……
Posted by Jerzy Ruzyllo at 10:25 AM |
Semiconductors
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Thursday, December 3, 2009
2009 IEDM is coming
The recognition of the IEEE International Electron Device Meeting (IEDM) as a prime technical/scientific event of the year is pretty well established in semiconductor community worldwide. Breaking with tradition, the 2009 IEDM will be held next week in Baltimore, MD, rather than in Washington, D.C. Other than this, IEDM 2009 projects itself as yet another meeting in the series worth attending.
Looking through the program it is quite obvious that the “CMOS era” continues to be in a full swing. Various structures/configurations/materials used to build transistors comprising a CMOS cell are considered (.e.g. nanowire based channels, high mobility III-Vs .....etc. ), but as a switch, CMOS does not seem to be challenged. At least not for now....
Posted by Jerzy Ruzyllo at 08:02 PM |
Semiconductors
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Tuesday, November 24, 2009
A non-semiconductor question....
Not exactly my territory, but I have a question… In my local paper I came across an information about “….proposed greenhouse gas emissions targets before the U.N. climate change summit meeting in Copenhagen…”. Why the need to control greenhouse gases emission is always mentioned in the context of climate change? Shouldn’t we control emission of these gases because they polute the air we breath? Climate change, or not? The permanent connection between CO2 emission in particular, and global warming (questioned by quite a few people, by the way) is blurring the picture with regard to this otherwise obvious need to control emission of gases which, unlike CO2, do not belong in the Earth's atmosphere.
Posted by Jerzy Ruzyllo at 06:48 PM |
Semiconductors
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Wednesday, November 18, 2009
Gate first, gate last
My previous blog with regard to the selectivity of cleaning of wafers which include HK+MG gate stacks (high-k gate dielectric and metal gate contact) reminded me about an issue which does not appear to be recognized as a major shift in CMOS processing paradigm which, in reality, it is. At least from the old-timer’s vantage point…
In short, no longer a classic “gate first” sequence, i.e. the process in which MOS gate stack is formed before source and drain are defined, is the only solution. With SiO2 as a gate dielectric and poly-Si gate contact, source and drain implantation and post-implantation anneal did not cause any problems in terms of gate stack degradation. With much less robust HK+MG gate stacks and strained channels the concern is that source and drain engineering steps could cause irreversible damage. The solution pursued by some advanced logic ICs manufacturers is a “gate last” approach. In this case source, drain and stressors are processed first and only then MOS gate stack is fit where it belongs. How interesting…
Posted by Jerzy Ruzyllo at 08:31 PM |
Semiconductors
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Thursday, November 12, 2009
Cleaning challenge - selectivity
“Selectivity” was always an issue in etch technology where etching of one material should not affect other materials on the surface of the wafer. “Selectivity” was not a top-of-the-list issue during standard cleaning operations of silicon wafers. That is not until MOS gates structures in state-of-the-art CMOS technology (45 nm and below) have become complex, multi-material mazes involving various high-k dielectrics with capping layers and metal gate contacts.
Regardless of whether such gate stacks involve dual-metal, single-dielectric (DMSD) or single-metal, dual-dielectric (SMDD) configurations the post-resist stripping clean up, that must follow gate stack delineation, has become a real challenge. Coming up with cleaning chemistry which will be benign with respect to such a divers range of materials is a real problem. Good times when during cleaning operations, even in the most advanced processes, we were dealing with just a silicon (substrate wafer and poly-Si gate contact) and silicon dioxide are gone.
Posted by Jerzy Ruzyllo at 08:59 PM |
Semiconductors
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Monday, November 2, 2009
Challenges in advanced wafer cleaning
Papers presented during recent ECS Semiconductor Cleaning symposium in Vienna (see previous entry), as well as other current semiconductor cleaning related publications identify numerous challenges this important part of semiconductor manufacturing process is facing.
For instance, as vertical dimensions of the device continue to shrink, the material losses and surface roughening during cleaning operations have become a real problem in surface preparation technology. The process of particle removal without material loss and pattern damage must involve serious tradeoffs. Physical aids such as megasonic agitation, potentially a key problem in terms of structural damage, is being re-engineered so that efficiency of the particle removal process will be maintained without pattern damage
Considering the fact that an atomic scale deterioration of surface morphology may have a "killer" effect on device performance, even seemingly the most benign elements of the cleaning sequence, such as DI water rinse, must be re-evaluated from this point of view.
Posted by Jerzy Ruzyllo at 07:38 PM |
Semiconductors
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Saturday, October 24, 2009
Semiconductor cleaning in Vienna
The 11th International Symposium on Cleaning and Surface Conditioning Technology in Semiconductor Device Manufacturing was held during the ECS Fall Meeting in Vienna (see complete list of papers presented). I will comment on the trends emerging in this important component of semiconductor manufacturing in the forthcoming blog(s).
Posted by Jerzy Ruzyllo at 06:27 PM |
Semiconductors
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