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Sunday, February 2, 2014

#275 Carbon is future

Among elements in group IV of the periodic table displaying strong semiconductor properties, which include carbon (C), silicon (Si), and germanium ( Ge), silicon continues to be a dominant force since the time it dethroned germanium some 50 years ago. Although this status quo is not expected to change for many years to come, I would like to point out to somewhat unexpected (yes, unexpected… did you hear about graphene some 10-12 years ago?) emergence of carbon as a problem-solving electronic material of the future.

With several allotropes, including graphite, diamond and amorphous phase, carbon covers unusually broad and highly diverse, for a single element, range of physical properties.  In electronics, graphene, nanotubes and diamond are the forms of carbon generating tremendous excitment regarding their possible application. Recently demonstrated form of carbon in between graphene and diamond, and known as diamane, which is a result of several layers of graphene collapsing under certain conditions into diamond matrix, also stirs imagination of device engineers and at the same time further demonstrate an immense potential of cabon. As all of this wouldnot be enough, carbon is also a component of silicon carbide (SiC) which has established itself as a key player in power device technology.

Well, I may not know exactly when, but I know that the era of carbon in semiconductor device engineering will descent upon us....


Posted by Jerzy Ruzyllo at 07:28 PM | Semiconductors | Link

Wednesday, January 22, 2014

#274 Slow transition to 450 mm

I was recently looking at the numbers defining an increase in the diameter of Si wafers used in IC manufacturing over the years starting with 1 inch wafers in about 1964 all the way to the transition from 300 mm to 450 mm (~18 inch) wafers anticipated for 2014-16 time frame. What caught my eye was an uneven pace at which progression was actually occurring. From 1 inch in 1960 to 6 inch (150 mm), wafer standards were changing roughly every 4.5 years. Then the pace did slow down and it  took about 8 years to switch from 150 mm to 200 mm and then another 8 or so years to complete standard change from 200 mm to 300 mm in about 2000. Some full 15 years may go by before transition from 300 mm to 450 mm will actually take place. 

Obviously, currently observed delay have little to do with technical barriers and much to do with cost of the transition. To me it means that the chip makers may not be fully committed yet to the dramatic increase in wafer diameter with all its consequences. It may also be taken as yet another indication that in the future semiconductor industry will go about its businesses in the very different way than in the past., i.e. transistor scaling and wafer diameter increase may no longer be a lead key to the icreased profitability.

Posted by Jerzy Ruzyllo at 10:41 PM | Semiconductors | Link

Sunday, January 19, 2014

#273 Problems with doping, cont.

Following on my previous comments regarding semiconductor doping, let me be more specific regarding problems with selective, i.e. localized, doping.


Consider, for example, wide-bandgap semiconductors. Diamond, which in theory is the best semiconductor around, is inherently p-type and cannot be readily converted into n-type. In contrast, in silicon carbide, SiC, p-type regions are very difficult to form as neither diffusion nor ion  implantation is effective.  In the former case it is because of extremely low diffusion coefficients of possible p-type dopants such Al  in SiC while in the latter extremely high temperature needed to activate dopants (1500 deg. C and above) is the lim itation. Did you notice that commercial SiC power diodes are based primarily on metal-semiconductor (Schottky) diode and not a p-n junction? Then, there is gallium nitride, GaN, in which n-type doping is simple, but p-type doping is very complicated. 


In general, selective doping of compound semiconductors is a challenge. Hence, when it comes to alterations of the conductivity type/doping level while building III-V electronic or photonic devices the task is typically accomplished by in situ doping during growth of the material rather than by implantation or diffusion into the material already formed.

Posted by Jerzy Ruzyllo at 09:43 PM | Semiconductors | Link

Sunday, January 12, 2014

#272 Problems with doping

Ability to control conductivity of semiconductors in general, and conductivity type (n- or p-type) specifically, is a cornerstone of any semiconductor device fabrication. As we all know, it is accomplished by introduction of the minute amounts of alien elements, known as dopants, into semiconductor structure. It can be done either homogenously during material growth or selectively by implantation or diffusion into the substrate wafer during device manufacturing.


Easy, right? Well, not necessarily. Ease with which silicon and germanium can be doped is misleading in the sense that these two are the only semiconductors, elemental or compound, in which doping is a straightforward matter. Among reasons for which other semiconductors do not readily lend themselves to selective doping the most important include: lack of elements which would act as either n- or p-type dopants in the case of some semiconductors, very low diffusion coefficient of potential dopants in some semiconductors, very high temperature  needed to render dopants electrically active, or in other words ionization temperature, and also inadequate thermal and structural robustness of many compound semiconductors which makes implementation of selective doping by either ion implantation or diffusion not practical. 


To be continued….

Posted by Jerzy Ruzyllo at 08:02 PM | Semiconductors | Link

Sunday, January 5, 2014

#271 Will EUVL follow footsteps of XRL?

Current discussion concerning "inevitable" end of the road for 193 nm lithography and resulting need to bring Extreme UV lithography (EUVL) to the mainstream IC manufacturing reminds me of the discussion going on in mid-80's regarding the need to speed up development of X-ray lithography (XRL). At that time it was abot "inevitable" inability of optical (UV) lithography to expose features below 1 micrometer.
Whichever way you look at it, challenges facing these two upstarts some 30 years apart are eerily similar in nature. Problems with complexity and resulting huge cost of sources, difficult to implement optics, highly specialized masks technology, etc., make challenges EUVL is facing now look very much like challenges XRL was facing in mid-80'.

As a  reminder, with all the innovations, photolithography did progress to the point where XRL was not really needed in mass production. Wouldn't the same happen to EUVL if it would turn out that we won't need to go down to geometries beyond exposure capabilities of current 193 nm lithography? Because alternative to transistor scaling path to ultra-low power logic would be found and adopted in mass production of next generation logic? Wouldn't then EUVL end up being sporadically used, exotic tool just like XRL is now?


Some 10 years from now will be a good time to look back and assess the situation in this regard.

Posted by Jerzy Ruzyllo at 05:32 AM | Semiconductors | Link

Tuesday, December 31, 2013

#270 2014

I would like to wish everyone visiting this site all the very best for 2014. It will be an exciting year for semiconductor aficionados with answers, or at least partial answers, to some key questions regarding future directions of semiconductor science and engineering emerging.

Posted by Jerzy Ruzyllo at 05:54 PM | Semiconductors | Link

Tuesday, December 31, 2013

#269 Semiconductor Surface Cleaning and Conditioning

 If you are interested in semiconductor surface cleaning and conditioning you may want to check a Focus Issue of ECS JSS devoted to this very topic. It is available on-line   and hard copy will follow this coming Spring. In the case you would be specifically interested in the status of gas-phase semiconductor cleaning technology you may consider reviewing my assessment of the progress in this area in this paper

Posted by Jerzy Ruzyllo at 12:30 PM | Semiconductors | Link

Sunday, December 15, 2013

#268 To scale or to go a different way?

Here is an interesting story related to my previous blog. It looks like the very benefits of transistor scaling down to low single digit nm gate length are questioned. Something that was bound to happen sooner or later finally came to haunt us - the cost rather than engineering is becoming a show stopper!

May be the time has come to consider a drastically different approach to transistor/circuit architecture as a problem solver? Such as for instance VeSFET/VeSTICs concept ? (see the blog#246).

Posted by Jerzy Ruzyllo at 03:44 PM | Semiconductors | Link

Sunday, December 15, 2013

#268 To scale or to go a different way?

Here is an interesting story related to my previous blog. It looks like the very benefits of transistor scaling down to low single digit nm gate length are questioned. Something that was bound to happen sooner or later finally came to haunt us - the cost rather than engineering is becoming a show stopper!

May be the time has come to consider a drastically different approach to transistor/circuit architecture as a problem solver? Such as for instance VeSFET/VeSTICs concept ? (see the blog#2.…)

Posted by Jerzy Ruzyllo at 03:32 PM | Semiconductors | Link

Sunday, December 8, 2013

#267 Down to 7 nm

Siting on the sidelines, I find it very interesting to follow over the years struggle of IC community with predictions of the evolution of digital ICs. Predictions, I might add, which quite often optimistically assume a success in working around barriers created by physics (which, actually, mostly do materialize). During my very early “semiconductor years” I distinctly remember 1 µm being considered to be almost insurmountable barrier in transistor scaling mainly due to the anticipated limits of photolithography. Some 25 years later, the very future of Si based CMOS below 22 nm gate length was questioned (see my comments in blog #103, Sept. 2, 2009). Incorrectly, because THE number is currently down to 7 nm which means that industry has a realistic plan with regard to how to get down to 7 nm gate length some 5-6 years from now. The number corresponds to about 35 silicon atoms which means that we will still have quite a few atoms to play with before we will really hit the bottom (good news is that “there is plenty of room at the bottom”, right?). But seriously, I share the opinion that before will get there, cost of the entire endeavor will force us to do things differently, i.e. we will have to find a different than transistor scaling path to ultra-low power logic.

Posted by Jerzy Ruzyllo at 09:01 PM | Semiconductors | Link

‹‹ ›› is the personal blog of Jerzy Ruzyllo. With over 35 years of experience in academic research and teaching in the area of semiconductor engineering (currently holding position of a Distinguished Professor of Electrical Engineering and Professor of Materials Science and Engineering at Penn State University), he has a unique perspective on the developments in this progress driving technical domain and enjoys blogging about it.

With over 2000 terms defined and explained, Semiconductor Glossary is the most complete reference in the field of semiconductors on the market today.

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