As semiconductr science and engineering is moving deeper into unchartered waters of fragile, almost exotic materials, most of them featuring very low resistance to thermal processes, plasma enhancement (PE) of deposition processes is becoming more and more instrumental.

First and formost, by bringing plasma emhancement (PE) to the deposition, allows Chemical Vapor Deposition (PECVD) processes to be carried out at the significantly lower temperature than the conventional CVD processes. It is an essential gain in mainstream BEOL (Back End of Line) sequences as well as in the case of various high-temperature sensitive inorganic III-V and II-VI compounds as well as organic semiconductors.

Second, PE may be used to catalyze chemical reactions during thin-film deposition allowing processe chemistries which would otherwise not be possible. For instance, range of possibilties of ALD (Atomic Layer Deposition) technology is significantly widen by bringing PE to the process (PEALD).

In short, as far as semiconductor manufacturing is concerned, PE is here to stay.

I find it very interesting to follow the discussion regarding choice of transistor architecture potentially the most effective in meeting requirements of future ultra-low power, ultra-high density digital integrated circuits. Sometimes it's been even referred to as the "transistors war". I commented on this situation on several occasions earlier  (e.g. blogs # 143, 175, 179). 

It appears that besides planar Fully Depleted and 3D Tri-gate (or MuG) FET architectures, an attractive alternative has entered the "race". It is a Vertical Slit Field Effect Transistor, or VeSFET. Based on simulation and early experiments, VeSFET could offer 3 orders of magnitude lower standby current, up to 16x higher transistor density, and significantly smaller power delay product than those listed above. To learn more about this truly innovative transistor architecture just type "vesfet" into any search box.

The most damaging contaminants in semiconductor manufacturing environment are particles. They can critically hurt any device fabrication process, but small geometry device are obviously especially prone to particle contamination related failure.

Next on the list, particularly in the case of semiconductors in which high temperature process are involved in device manufacturing (e.g. Si and SiC), are metallic contaminants with Fe, Al, Cu being the most common.

Then come ubiquitous (because they are present in ambient air as well as in water)  organic contaminants. Difficult to control in the ambient such as clean-rooms or storage and shipping boxes, but relatively easy to remove from the wafer surface.

In the light of the above it is not surpisingg that cleaning operations are the most frequent processing steps in semiconductor manufacturing. Very thoroughly executed steps are particularly essential in the caese of high-quality, .i.e. very low defect density, crystalline substrates. In the case of low quality substrates, role of surface contaminants is somewhat diminished as device performance will be mostly affected by the defects in semiconductor.

In general, acceptable manufacturing yield is not possible without frequently performed cleans. There are situations, however, where  unnecessary cleaning, i.e. cleaning introduced into the process sequence "just in case", can do more harm then good. So, knowledgeable use of cleans is essential

This is a word of wisdom coming from somebody who over the years put much time and effort into a semiconductor cleaning research.
 

The fact is that not only semiconductor surfaces, but also near-surface regions strongly interact with ambients to which semiconductor wafer is exposed. While the effect itself is well recognized, appreciation of its implications quite often does not seem to be there in spite of the fact that they may account for difficult to control variability in device manufacturing processes.

Take for instance p-type silicon which by definition is boron doped (in the case you don't remember, boron is the only element making Si p-type). Boron dopant atoms in the near-surface region of silicon may be rendered inactive (i.e. not producing free hole) by interaction with hydrogen. Boron de-activating hydrogen may be introduced into the near-surface region of silicon during polishing operation carried out during wafer manufacturing. But it doesn't have to be that complicated as hydrogen can readily penetrate near-surface Si during routine D.I. water rinsing operations for instance! Would you expect such a routine operation as wafer cleaning and rinsing to alter conductivity of Si good few nanometers under the surface? Well, it does...

Fortunately, interaction of hydrogen with silicon can be labaled "easy in-easy out" as modest thermal treatments will drive most of hydrogen out of Si near-surface region. Still, it's good to be aware of such interactions. You may want to check our old J.A.P. paper  ( http://jap.aip.org/resource/1/japiau/v83/i4%26page=3  , pages 2297-2300) to see a more complete story of near-surface boron de-activation by hydrogen.

An interaction of hydrogen with p-type silicon is used just as an example here. The real intention of this story is  to convince you  that semiconductor surfaces and near-surface reagions live their own lives which are very different from what's goingb on in the bulk of the semiconductor material.
 

At the time where thickness of features in advanced semiconductor devices is in the range of single nanometers, characterization of  materials systems incorporating such features, as well as monitoring of fabrication processes that produce them are the real challenge. How do you, for instance, detect presence and estimate thickness of about 2-3 nm thick layer of high-k dielectric squeezed between metal and silicon?  Or visualize  layers of divers materials, each 1-2 nm thick, in a superlattice? 
 
Well, TEM to the rescue.... Transmission Electron Microscopy (TEM) is about the only technique that can accomplish both of the above and more. TEM projects on the imaging device an image of the interactions of the electrons transmitted through the sample. The result is an image of the cross-section under investigation featuring atomic-level resolution. To make it possible, however, technically complex and time consuming sample preparation procedure must be precisely executed. It's worth an effort, however, considering an outcome in the form of an atomic-level resolution images of nano-structures.

As an admirer of silicon (I consider silicon to be one of the great gifts Mother Nature offered us), I am somewhat sorry to see the role of Si in semiconductor power electronics diminishing slowly, but steadily. Power semiconductor devices, i.e. devices capable of handling thousands of Volts and Amps often in harsh environment and at elevated temperature, constitute critically important segment of semiconductor electronics. New demands are imposed by requirements regarding compactness and low weight of power components of mobile comunication devices, electric cars, aircrafts, spacecrafts, etc., etc.

For decades silicon was an unintended hero of power electronics. Unintended because for all practical purposes Si is unsuitable for power device applications. With energy gap of 1.1 eV, which limits Si usefulness to temperatures below 150 C, relatively low breakdown field and average thermal conductivity, silicon is not much of the "power semiconductor". In spite of it, for years Si did, and in some applications will continue to do, bravely carry the load of power electronics as the only semiconductor rendering itself to the manufacture of commercial power discrete devices (diodes, transistors, thyristors) and integrated circuits.

It was this way because until quite recently the real power semiconductors i.e. silicon carbide (SiC, energy gap 3.2 eV) and gallium nitride (GaN, energy gap 3.0 eV) where simple not there in terms of single-crystal quality and manufacturability. Now, however, they are there which means that the "silicon era" in power electronics is bound to come to the end.

As several of my earlier postings indicate, I am a strong believer in the potential of silicon wafers as substrates in semiconductor device engineering. Whichever way you want to look at it, Si wafers are by far the highest quality, large diameter, relatively cheap, and very readily available substrates which can be used in device engineering well beyond silicon technology. In particular, for those semiconductors which either do not have their native substrates at all (e.g. GaN) or do not have native substrates that feature large diameter (200 mm and above), silicon wafers are the substrates of choice. 
 

The perennial challenge heteroepitaxial integration of Si substrates with other semiconductors is facing is the problem of a mismatch of crystalollgraphic lattices. However, under the increasingly heavy pressure from device community it was only a matter of time for the heteroepitaxial technology based on Si substrates to become a commercial reality. Not long ago, in the blog #231 to be exact, I was marveling about the fact that big logic ICs manufacturesr figured out the way to form device quality InGaAs films on 300 mm Si wafers. Equally encouraging is commercial availability of GaN on 150 mm Si wafers reported earlier.

To summarize, long live silicon!

 

For a change, this time it is not about a technical issue, but still very much semiconductor related one. It is about a word “semiconductor” in various languages.

It occurred to me that only in Roman languages (French, Spanish, Italian…)  as well as in English, half-conducting ability of certain solids is referred to using Latin words "semi", which means "half", and also originating from Latin word “conductor” meaning of which is obvious.  

By education and many years of professional experiences I am all about semiconductors. On the other hand, I am kind of fanatical about downhill skiing. Until recently, these too passions of mine did not really interfere with each others at any level. Silicon surface engineering and quantum dot films do not mesh with skiing. On the other hand, sharp edges, smooth base, properly releasing bindings and a pleasure of being immersed in pure nature don’t have much to do with semiconductors.

Progress in various technical domains in the field of semiconductors can be driven by the very different needs. Consider silicon substrate wafers for instance. In logic ICs and memories featuring ultra-small geometrical features it is critically important that the wafers maintain mechanical stability during processing. Otherwise, reproducible resolution of the pattern transfer operations cannot be assured due to the possible variations of the depth of focus as a result of wafer bowing or warping. Hence, as the wafers are getting larger, they are also getting thicker – close to 1,000 μm in the case of 450 mm wafers. Resulting increased cost of silicon in this case is not welcome, of course, but it must to be accepted as otherwise process would not work.