The term “nanotechnology” has become a highly recognizable, but, outside of the scientific community, rarely fully understood symbol of everything that is ultimate in science and technology. What adds to the apparent identity problem is that the term “nanotechnology” means, and rightly so, different things to the scientists representing different scientific domains.

Among various ways of looking at “nanotechnology” the one which I use for the purpose of explaining the fundamentals distinguishes between “hard nanotechnology” and “soft nanotechnology”. The former is obviously concerned with physics, materials, material systems engineering and is used in reference to advance technical endeavors such as high-end integrated circuits (32 nm technology generation for instance), 2D material systems (e.g , quantum wells), 1D (e.g., nanowires); and zaroD (e.g.; quantum dots). The latter is concerned primarily with chemistry, biology, medicine, life sciences in general. Both manipulate the matter at the atomic and molecular level, but for the different purpose (quite often using the same tools, though).

Yes, it is a simplistic interpretation of the phenomenon known as nanotechnology, but my experience is that at the very fundamental level it seems to be working very well.

Where do you go when you need just a substrate? You don't care about its chemical composition, or crystallographic structure, electrical conductivity, etc. You just need a thin, very clean, temperature resistant, chemically resistant, mechanically sturdy piece of material featuring very smooth surface. And you need, let's say, 150 cm² of it, or may be even 500 cm², and you don’t want to spend thousands of $$ to get it. And, in addition, you want it to be compatible with a standard photolithographic pattern definition tools.

Without too much of the fanfare the terminology used to identify various classes of semiconductors is gradually evolving as the semiconductor landscape is changing.  In terms of crystallographic structure for instance, terms "ordered" and "disordered" semiconductors are often being used instead of the more traditional terms "crystalline" and "non-crystalline" (amorphous) semiconductors. As the latter refer to the three-dimensional arrangements of atoms and to the corresponding geometry of physical interatomic bonds in the material, they do not adequately reflect the nature of organic semiconductors, for instance.

My experience shows that in order to cover the entire semiconductor field these days it is helpful to add a sub-class of "nano-ordered" semiconductors to the above "ordered-disordered" scheme.  The term is used in reference to the self-contained, crystallographically ordered semiconductor material systems which due to the extremely confined geometry (at least in one dimension less than about 5 nm - I agree, this number is rather arbitrary, but you are getting the idea...) feature different physical properties than their bulk counterparts. Obviously, we are talking  here nanowires, nanotubes, quantum dots, graphene, etc.

I am glad to be back after the long break as there are several interesting issues on which I would like to comment.
 
First, in the spirit of my earlier post (”Era of materials and elaborate material systems” of January 12, 2010) a quick observation with regard to the still expanding pool of elements from which semiconductor researchers and engineers are drawing to build better performing devices. Most you may not remember it, but, as I was commenting earlier, for years it was all about silicon, oxygen, nitrogen, and aluminum. It was all that was needed to fabricate most of the devices including early ICs. Then the copper joined in, then … Well, as the needs are growing and complexity of devices increases rapidly, it seems as almost every element in the periodic table is of potential interest to the semiconductor community these days.

How about gadolinium oxide (Gd₂O₃ ) also know as gadolinia? To the old-time “semiconductorer” such as me it sounds rather exotic. I will be back with some more specific comments on gadolinia soon.

It’s been a while since I posted the last blog. While on sabbatical and on the go since the beginning of the Spring semester I don’t get much time to do fun things such as occasional blogging. 

At various times over the years, various elements of semiconductor science and engineering were defining progress. Not long ago, when silicon was a sole ruler, the progress was riding mainly on the shoulders of improvements in process technology. At that time, developments that were punctuating the advancements were basically synonymous with what was going on in high-end logic and memory IC technology.

In the very old days ion implantation pushing aside doping by diffusion was a hit (even earlier diffusion replaced alloyed junctions by the way), then RIE came about as a savior in etch technology, then its HDP version, then CMP, supercritical fluid cleaning, etc.  And of course photolithography with its developments was continuously looming over the horizon –steppers, g-line, i-line, excimer lasers, phase shift masks, immersion lithography were defining the progress.

While all this was happening not much was changing in materials (with an exception of copper replacing aluminum as an interconnect material) and device configuration. It was all based on silicon (single-crystal Si, poly-Si, SiO₂, Si₃N₄) and planar CMOS was a device benchmark.

During the last decade or so the paradigm has shifted significantly. It is all about the materials and elaborately configured materials systems these days. Even the latest process technology related breakthrough, introduction of ALD into the mainstream manufacturing, was driven solely by the material related needs (introduction of high-k gate dielectrics). Other than that, on both ends of the line, front and back, high-end material and device engineering determine the progress. For instance, high mobility channel materials, SiGe and SiC stressors, high-k dielectric gate stack engineering, new generation of ILDs , TSVs, etc,etc.…. Even silicon substrate itself must be heavily engineered to meet emerging needs. Furthermore, needs of photovoltaics, organic semiconductor technology, printed large area electronics and photonics, flexible substrates, MEMS/NEMS, opportunities in advancements in TFT technology, 2D (graphene for instance), 1D (nanowires), zeroD (nanodots) material systems, ferromagnetic semiconductors  etc. etc., spread semiconductor innovation efforts well beyond mainstream digital IC territory.

All this is breathing fresh air into semiconductor research. It is no longer that one must have 300 mm wafer capability, at least class 10 clean-room and 193 nm exposure tools to do research that have any relevance. The window for innovations is wide open and the reliance on the highest end tool is lesser than in not too remote past. Let’s hope funding will be sufficient to allow semiconductor R&D community to fully spread its wings

The recognition of the IEEE International Electron Device Meeting (IEDM) as a prime technical/scientific event of the year is pretty well established in semiconductor community worldwide. Breaking with tradition, the 2009 IEDM will be held next week in Baltimore, MD, rather than in Washington, D.C. Other than this, IEDM 2009 projects itself as yet another meeting in the series worth attending.