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Sunday, May 30, 2021

#470 More on the role of MOS gate capacitance

A precondition for the properly working MOSFETs (Metal-Oxide-Semiconductor Field Effect Transistors), which rule digital IC technology regardless of technology node, is adequate capacitive coupling between gate contact and silicon. In other words, density of MOS gate capacitance needs to be sufficiently high to keep transistor work while it is being reduced in size to pack more transistors per unit area of the chip.

 

Seeing evolution of the MOSFET during the last 15 years through the prism of the density of MOS gate stack capacitance, the following three stages can be identified:  (i) replacing thinned to the limit SiO2 as a gate oxide with higher dielectric constant material to allow increased physical thickness of the gate dielectric, (ii) modifying transistor architecture and using “fin” configuration to increase gate area at the reduced transistor foot print, and (iii) employing nanoscaled silicon in the form of stacked-up nanosheets to address challenges facing next generations of MOSFET-based digital electronics.

 

Some more on the role of MOS gate capacitance in the blog posted on January 17, 2021

 

Posted by Jerzy Ruzyllo at 10:00 AM | Semiconductors | Link


Sunday, May 9, 2021

#469 Confusing terminology

If you find news about “10-7-5-2 nm technologies” confusing, you are not alone. As a neutral observer with interest in #semiconductorengineering, I don’t see how current “nm nod” terminology is serving any useful purpose other than creating opportunities for marketing blitzes.

 

Nanometer is a unit of length. So, it makes sense only in reference to specific geometrical features of the transistor or interconnect scheme, and not necessarily in the context of "nm node" business endeavors, right? Well, you would think so.

 

In the world of advanced digital IC it seams to be free for all. The number of nm, whatever it represents, needs to be smaller. It’s all that matters. “5” is better than “7”, right? Well, how do we know? What does 10 nm nod of company X mean? How does it compare to 7 nm nod of company Y? Is 10 nm necessarily not as good as 7 nm in terms of manufacturability, reliability, performance in real circuits applications, and cost? Who knows? Some of those chips are not on the market yet.

 

For quite some time I was naively thinking, again as a neutral observer, that the technology node refers to transistors gate length. Only not long ago I realized that technology nodes and gate length parted ways somewhere around 32 nm- 45 nm. But how can one rationally compare technologies, if depending on the company, nanometer measures different things? Half-pitch? Pitch? Separation between transistors? Some numbers are referring to geometries of interconnects scheme, some to transistor itself? For instance, is there any feature sized at 2 nm in the recently announced by IBM 2 nm technology breakthrough?

 

Why don’t we adopt for good a number of transistors per unit area of the chip (not per chip) as a measure of technological complexity of the chip, and hence, technology advancement? It was suggested by knowledgeable people on several occasions in the past and is often provided. And the number defining circuit density will grow with the progress in technology as opposed to “technology nods” defined as 10, 7, 5, 2, … then 1(?), then… what?

 

 

 This entry is a continuation of the blog posted on January 10, 2021.

Posted by Jerzy Ruzyllo at 03:48 PM | Semiconductors | Link


Sunday, April 11, 2021

#468 III-VI compounds, cont.

 In the previous blog two materials, gallium oxide, Ga2O3, and aluminum oxide Al2O3,  were identified as an example of III-VI compounds which are featuring very different characteristics. What is interesting here is that while both are oxides, one of them is semiconductor (Ga2O3), and the other one (Al2O3) is an insulator which is an example of how intriguing chemistry of III-VI compounds affects their electronic properties.

 

Gallium oxide is a wide band gap semiconductor (4.8 eV) with a great potential in power switching and RF electronics. Aluminum oxide (in the single-crystal form know as sapphire, by the way) is a clear-cut insulator with a band gap exceeding 7 eV and excellent thermal and chemical resistance. It is used as a substrate for both GaN and silicon single crystal films (Silicon-on-sapphire, SOI). Both belong to the class of transparent oxides, but gallium oxide is a transparent conductive oxide (TCO) while aluminum oxide is not. Both are commercially available in the form of large diameter wafers which is a clear indication of the role they play,each in its own way, in practical commercial applications.

 

The point here is not to elaborate on the science behind binary semiconductor compounds, which is beyond the scope of this blog, but to shed some light on the existence and importance of  III-VI compounds and to point to the reasons for which III-VI compounds are not seen the same way IV-IV, III-V, and II-VI compound semiconductors are seen (find more on compound semiconductors here).

  

Either way, III-VI compounds are here to stay, and as such should be appropriately accounted for in our scientific, technical and educational deliberations. And this is only an example of what elements from semiconductor periodic table, in seemingly endless binary, ternary and quaternary combinations, can contribute to materials science and engineering.

Posted by Jerzy Ruzyllo at 09:44 PM | Semiconductors | Link


Sunday, April 4, 2021

#467 III-VI compounds

Members of semiconductor community, whether associated with teaching, research, or manufacturing, are familiar with man-made semiconductor compounds formed using elements from groups II to VI of the periodic table. The IV-IV compound semiconductors (SiC, SiGe), III-V compound semiconductors (e.g. GaAs, InAs, GaN, etc.), as well as II-VI compound semiconductors (e.g. ZnO, CdTe, CdSe etc.) are well-known and most of them are broadly used in various practical applications, whether electronic or photonic.

 

Another class of compounds based on the same elements of the periodic table but in III-VI combination, is seen somewhat differently than those listed above. One of the underlying reasons could be different than in the case of those other compounds, known as compound semiconductors, number of valence electrons shared by the contributing elements and involved in interatomic bonding responsible for the cohesion of the compound in the case of III-VI materials (nine instead of eight). The result is more complex interatomic bonding scheme leading to the more divers electronic properties among III-VI compounds as compared to IV-IV, III-V and II-VI compounds displaying mostly semiconductor characteristics. In contrast, some among III-VIs are featuring strong semiconductor characteristics, e.g. gallium oxide Ga2O3, while others, most notably aluminum oxide Al2O3, is a quintessential insulator. As a result, III-VI compounds are not being referred to as III-VI semiconductors. 

 

A bit more on this topic next time…

 

Posted by Jerzy Ruzyllo at 05:26 PM | Semiconductors | Link


Sunday, March 28, 2021

#466 Semiconductor material selection criteria

Often encountered question is why certain semiconductor material is suitable for any given device application while other is not. List of the device implications of select physical characteristics of semiconductor materials is fairly long (see Guide to Semiconductor Engineering (worldscientific.com), so here are just three key characteristics. 

 

Energy gap width -  in electronic devices wide bandgap (e.g. SiC) allows better handling of power and temperature. In photonic devices bandgap defines light absorption and emission characteristics. A wide bandgap semiconductor (e.g. GaN) is needed to emit high energy (shorter wavelength) radiation such as blue light.

 

Type of energy gap – indirect bandgap semiconductor (e.g. Si) features inefficient radiative recombination which means that, without employing special “tricks”,  it is not a material suitable for the manufacture of light emitting devices. Direct bandgap semiconductors on the other hand are the materials we use to make light emitting devices such as LEDs and lasers.

 

Electron mobility – determines speed of electronic device operation in both digital and analog applications.

Posted by Jerzy Ruzyllo at 12:07 PM | Semiconductors | Link


Sunday, March 21, 2021

#465 Thirty years ago: March 1991

The cover story of the March ’91 issue of Solid-State Technology magazine was devoted to the large diameter silicon wafers. At that time “large” meant 200 mm wafers which were scheduled to be used in commercially significant numbers in the 1991-92 time frame. Well, 300 mm and 450 mm wafers happened between then and now, but 200 mm continue to be a go to substrate in various commercial applications.

 

What caught my attention while reviewing contents of the March ’91 issues of the Journal of the Electrochemical Society and IEEE Electron Device Letters was a significant number of papers concerned with GaAs (and its derivatives) processes and devices. And yes, I recall times some 30 years ago or so, when GaAs was seen as a semiconductor material of the future, sooner or later replacing silicon in all key electronic applications. Well, as we all know it didn’t happen.  

Posted by Jerzy Ruzyllo at 11:23 AM | Semiconductors | Link


Sunday, March 14, 2021

#464 Non-contact, in-line, real-time RF wafer monitoring

Electrical measurements of semiconductor materials and devices have always been, and will continue to be a key characterization methodology in semiconductor device engineering. When properly applied, electrical characterization can unequivocally determine quality of material and predict performance of device to be built using this material (trust me, I know it, I used electrical characterization in my research for some  45 years)

 

A challenge in this specific application is to perform electrical characterization without contacting a product wafer, or other crystalline semiconductor material, and without any interference with its characterized surface. In other word, the challenge is to perform measurements in the totally noninvasive fashion compatible with the needs of in-line, real time monitoring of processes used to manufacture semiconductor devices.

 

New opportunities in the area are provided by non-contact, in-line, real-time method based on the use RF radiation. If interested, and may be interested in being involved in this project,  take a look at the Defect Specific Lifetime Analysis (DSLA) method described here: GEKA ASSOCIATES (gekallc.com)

 

Posted by Jerzy Ruzyllo at 08:40 PM | Semiconductors | Link


Sunday, March 7, 2021

#463 Non-semiconductor substrates

There are several semiconductor device applications in which substrates in the form of rigid, electrically conductive semiconductor wafers are not needed, or not desired. In such cases, insulating substrates are employed to provide mechanical support for semiconductor devices built on their surfaces using broadly understood thin-film technology.

 

In the case electronic and/or photonic devices require an insulating substrate featuring outstanding optical, mechanical, and chemical characteristics, sapphire is the first choice. Sapphire is a single-crystal (hexagonal) form of aluminum oxide Al2O3, which features substrate properties that are highly conducive with the needs of several key electronic and photonic semiconductor devices.

 

In the case when single-crystal material is not needed as an insulating substrate, glass is a solution. As a result, glass is the most common substrate in thin-film semiconductor device technology. It offers insulating properties, transparency to light, and adequate mechanical stability.

 

Both sapphire and glass substrates are mechanically rigid and as such are used only in semiconductor devices and circuits which are not subject to bending, flexing or stretching. When flexibility of the substrate is needed, bendable and rollable plastic films are the first choice

 

Look for more information on non-semiconductor insulating substrates used semiconductor device engineering in the Guide to Semiconductor Engineering (worldscientific.com)

 

Posted by Jerzy Ruzyllo at 08:32 PM | Semiconductors | Link


Sunday, February 28, 2021

#462 Thirty years ago: February 1991

Two papers in February ’91 issue of IEEE Electron Letters that attracted my attention were concerned with very different topics. First was a paper by my Penn State colleagues describing successful realization of transistor action in the thin-film diamond Field-Effect Transistor. The other one demonstrated significantly increased hole mobility in strain-controlled Si-Ge Modulation-Doped FET. It was an early indication of the possibilities to improve device performance by employing strain in the crystal lattice induced by SiGe.

 

At the material/process end of semiconductor research spectrum Journal of the Electrochemical Society in its February ’91 issue reported on the Reactive Ion Etching of Indium-Tin Oxide (ITO) which since then became number one transparent conductor broadly used as a contact material in various photonic devices. Also, published in this issue paper concerned with the effect of oxygen concentration on lifetime in magnetic Czochralski (CZ) grown single-crystal silicon was a confirmation of advantageous role magnetic field is playing in the CZ processes.

Posted by Jerzy Ruzyllo at 07:49 PM | Semiconductors | Link


Sunday, February 14, 2021

#461 Engineered wafers

 In the high-end silicon device manufacturing homogenous Si wafers, commonly referred to as bulk wafers, need to be engineered further to meet specific device related requirements. Directions in which wafer engineering may proceed depends on type of device wafers will be used for and include the following solutions.

 

Denuded zone formation Term “denuded zone” refers to the very thin part of the wafer immediately adjacent to its top surface from which some excessive structural defects and/or alien elements (contaminants) are displaced into the bulk portion of the wafer by means of the gettering processes.

 

Epitaxial extension Process of epitaxial deposition allows formation of the very-thin layer of single-crystal material in such way that the crystallographic structure of the deposited film exactly reproduces crystallographic structure of the substrate, yet the film is chemically purer and if grown sufficiently thick may feature the surface that is less defective than the surface of the substrate (e.g. formation of thick SiC epilayers on SiC).

 

Strained-layer heteroepitaxy is yet another technique that is being used to engineer substrate wafer toward building into it desired characteristics which in this case is a strained top surface layer.

 

Wafer bonding is a process which permanently bonds (fuses) two wafers into a single mechanically coherent substrate without using adhesives.  This versatile technique allows formation of semiconductor substrates which are impossible to obtain using other methods.  

 

For more information regarding wafer engineering see Guide to Semiconductor Engineering (worldscientific.com)

Posted by Jerzy Ruzyllo at 05:43 PM | Semiconductors | Link


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Semi1source.com/blog is a personal blog of Jerzy Ruzyllo. He is Distinguished Professor Emeritus in the Department of Electrical Engineering at Penn State University. With over forty years' experience in academic research and teaching in semiconductor engineering he has a unique perspective on the developments in this technical domain and enjoys blogging about it.




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